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kulp
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This belongs with commit f1517c0.
Add the `-DVERILATOR` option (disabled by default) and wire the Verilator simulator into the CMake build conditionally.
Introduce the Verilator-based simulator that runs tenyr code through the Verilog implementation. The simulator: - provides serial text output via simserial.v - supports -v verbosity levels matching tsim (0-4) - shares disassembly and register dump code with tsim via asm.c - loads .texe (obj) binary format The main simulation loop includes proper halt detection: - Checks for $finish instruction (0xffffffff) at the S0 state boundary using a two-phase finish_pending flag, letting the instruction execute through S3 so its data memory access is traced before halting - Checks the core halt signal (err_i | rty_i) at every cycle - Updates prev_state after halt checks so the S6->S0 transition is detected correctly
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Running on Verilator may or may not give tenyr an obvous immediate advantage, but given how quickly its generated C++ code can run, it seems a reasonable way to introduce a cycle-accurate simulator alternative to the (time-agnostic) functional simulator that is
tsim.With a long-running Fibonacci (argument 30), the Verilated
vsimas of 981425b is about 7x slower thantsim.