docs(arxiv): XC7A100T LUT count is 63,400 — the docs give its flip-flop count - #2281
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Both arXiv sources described the platform as "QMTECH XC7A100T-1FGG676C (Artix-7, 126,800 LUTs, 240 DSP48E1)". 126,800 is that part's flip-flop count; its LUT count is 63,400. One line each in docs/arxiv-submission/trinity-gf16.tex:296 docs/arxiv-trinity-gf16-draft.md:116 The replacement was verified against this repo before being propagated, not taken on the source PR's word: compiler.rs:10041, partition.t27:36, power_analysis.t27:67, stdlib.t27:159 and ternary_isa.t27:285 all encode 63400 LUTs / 126800 FFs. That is the standard 7-series decomposition (15,850 slices x 4 LUT, x 8 FF), and the doc's own "240 DSP48E1" is XC7A100T's DSP count, so only the column was wrong. appendix_I.md:196 already uses 126800 as an FF denominator. Source: PR #2081, which bundles four fixes. This is one of them. Deliberately excluded: specs/numeric/formats_catalog.t27 -- the "FPGA 35/35 at 323 MHz Artix-7" claim. A maintainer adjudicated it on master in 59ae2ae; #2081 proposes a different resolution. Unresolved human question, #2081 stays open. bootstrap/src/main.rs and .github/workflows/fpga-build.yml -- master already has both fixes in more complete form (openXC7/nextpnr-xilinx, --recursive --depth 1, plus bbasm). #2081's README RED rows -- re-measured on 2026-08-20, every figure in the replacement text is now false: fpga-synthesis succeeds, last green is 2026-08-19T19:10:25Z (not 2026-04-14), run totals are 50/932/15 over 997 (not 36/842/3 over 881), and fpga-bitstream runs, succeeds, and uploaded a 7,049-byte .bit on 2026-08-19. Today's red is fpga-conformance, a different job. The README's FPGA status is not re-verified here. Found but not fixed: appendix_F.md:14, appendix_I.md:195 and ch28.md:87 give the LUT count as 101,440 -- a different wrong number (the logic-cell figure).
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Closes #2280. Source: #2081 — this is one of that PR's four fixes, and #2081 stays open.
The change
Two lines. Both arXiv sources described the platform as:
126,800is that part's flip-flop count. Its LUT count is63,400.docs/arxiv-submission/trinity-gf16.tex:296docs/arxiv-trinity-gf16-draft.md:116Plus a
docs/NOW.mdentry.The replacement number was verified, not trusted
A correction that swaps one unbacked number for another is worse than the
original, so
63,400was checked against this repository before beingpropagated. Every place the tree encodes this part agrees:
bootstrap/src/compiler.rs:10041-10042luts: 63400, ffs: 126800specs/fpga/partition.t27:36fpga_node(.., 63400, 126800, 135, 240, 300)specs/fpga/power_analysis.t27:67-68max_luts = 63400,max_ffs = 126800specs/fpga/stdlib.t27:159-160luts = 63400,ffs = 126800specs/fpga/ternary_isa.t27:285luts < 63400TASK.md:116XC7A100T (63400 LUTs, 90% warning)Two independent checks:
8 FFs per slice gives exactly
63,400and126,800.240 DSP48E1isXC7A100T's DSP count — only the column was wrong.
And a utilization report already in the tree uses 126,800 as the FF
denominator:
docs/phd/appendix_I.md:196readsFF: 27 / 126800.Deliberately excluded from #2081
1. The
35/35 at 323 MHz Artix-7claim inspecs/numeric/formats_catalog.t27.A maintainer adjudicated this on master two days ago in
59ae2aeee; #2081proposes a different resolution. That is a factual dispute for a human, it is
not settled here, and #2081 remains open for it. That file is untouched by
this PR. Nothing here is evidence for either side.
2. The
synth.ys-DSIMULATIONfix (bootstrap/src/main.rs) and thenextpnr repo fix (
.github/workflows/fpga-build.yml). Master already hasboth, in more complete form —
openXC7/nextpnr-xilinxwith--recursive --depth 1, and it also buildsbbasm. Re-landing #2081's version would be aregression.
3. #2081's README RED rows. These were mergeable, but re-measuring against
the GitHub API on 2026-08-20 shows the replacement text is now false in every
particular:
fpga-synthesisCI job failing2026-04-1432291533826, master)fpga-bitstreamskipped behindneeds: fpga-synthesis.biton 2026-08-19The workflow is red again today, but from
fpga-conformance— a differentjob. Those figures were true when written on 2026-08-11; they are not true
now. Landing them would replace two roughly-right rows with three rows whose
every supporting number is wrong.
The README's FPGA status is therefore not re-verified by this PR. It may
still be wrong in its own way — it is simply not made worse.
Found but not fixed
docs/phd/appendix_F.md:14,docs/phd/appendix_I.md:195anddocs/phd/ch28.md:87give XC7A100T's LUT count as101,440— a differentwrong number (the marketing logic-cell figure,
63,400 x 1.6). Out of scope;left for its own PR.
No hardware
The LUT figure is a datasheet property of the part, cross-checked against this
repo's sealed board definitions. It is not a measurement of any design, and no
board was run for this change.