ci(fpga): the vacuous greens are gates again - #2242
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Self-audit over the first full-green master run found three jobs that were green while verifying nothing, each confirmed by two independent refutation passes. fpga-formal: .sby files used indented pseudo-blocks sby does not parse (the bmc task saw no [engines] and died before any solver), [files] paths escaped the workspace, the 'if sby|tee' tested tee without pipefail so PASS was unconditional, and continue-on-error capped the job green over everything. fpga-conformance: bare -g2005 compiled 0 of 32 testbenches and the failure was a warning; the 'CLEAN' verdict in the summary is a static JSON field echoed as if computed (vvp lane: #2241). fpga-lint: the repo's own readiness tool printed NOT READY and exited 0; 1/32 invalid Verilog was a warning. All four now fail when they find nothing: canonical per-line sby task conditionals with local paths, pipefail + no continue-on-error + FAIL fails the step, -g2012 -DSIMULATION + exit 1, lint exit 1, synth-readiness bails on NOT READY. The expected honest red on lint has a named cause: a live gen-verilog regression (#2240) that the warning-gate absorbed within 40 minutes of the 32/32 claim. Closes #2239.
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# Conflicts: # docs/NOW.md
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PR DashboardGenerated at: 2026-08-19 19:11:53 UTC
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# Conflicts: # docs/NOW.md
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…nt" (#2362) fpga-lint reported 32/32 green on the same artifact iverilog compiles 4/32. Re-measured on `fpga-verilog` of run 32464326319 and again on run 32511534193: read_verilog+hierarchy 32/0, iverilog -g2012 4/28, same four survivors. The cause is reachability, not depth -- yosys enters a function body only at a call site, and 406 of the 485 functions in those files have none. `synth -top` was measured too: 31/1, flagging zerodsp_top for a missing submodule, certifying the other 27. What the job runs is unchanged. What it claims is corrected: the display name, the step summary, the **Result:** headline and the fpga-report row, which said "Lint (all 31 modules)" -- wrong depth and wrong count. scripts/ci/check_fpga_lint_claim_matches_depth.py holds it, wired into gate-topology with its own --self-test. It reads the yosys passes out of the step's -p script and requires the label, summary and report row to name them, so deepening the command forces the claims to move with it. No check was added that catches the 28 -- that turns the job red until #2325 lands and is a gate-policy decision, not a wording fix. Closes #2326 Refs #2325, #2241, #2242, #2239 phi^2 + 1/phi^2 = 3 | TRINITY Co-authored-by: Claude <claude@anthropic.com>
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Closes #2239. Refs #2240 #2241. Three jobs were green while verifying nothing (formal: zero properties, three independent always-green layers; conformance: 0/32 compiled behind a warning, no vvp; lint: NOT-READY + invalid Verilog as warnings). All now fail honestly. Expect fpga-lint to go red on master until the live codegen regression #2240 is fixed — a refusal on the record beats a vacuous green (repo doctrine). docs/NOW.md updated.
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