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fix(gen-verilog): nested struct field access resolves to one cumulative part-select - #2248

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fix/nested-field-partselect
Aug 19, 2026
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fix(gen-verilog): nested struct field access resolves to one cumulative part-select#2248
gHashTag merged 4 commits into
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fix/nested-field-partselect

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Closes #2240. The live regression behind the expected honest-red lint: a field-access base fell through to name-flattening and glued an identifier fragment onto a part-select. Chain now resolves to a cumulative part-select; 0 glued sites, yosys parses fifo.v, full smoke set 32/32 — the honest gates from #2242 can be green for real. M5 performed. docs/NOW.md updated.

🤖 Generated with Claude Code

Self-audit over the first full-green master run found three jobs that were
green while verifying nothing, each confirmed by two independent refutation
passes. fpga-formal: .sby files used indented pseudo-blocks sby does not
parse (the bmc task saw no [engines] and died before any solver), [files]
paths escaped the workspace, the 'if sby|tee' tested tee without pipefail
so PASS was unconditional, and continue-on-error capped the job green over
everything. fpga-conformance: bare -g2005 compiled 0 of 32 testbenches and
the failure was a warning; the 'CLEAN' verdict in the summary is a static
JSON field echoed as if computed (vvp lane: #2241). fpga-lint: the repo's
own readiness tool printed NOT READY and exited 0; 1/32 invalid Verilog
was a warning.

All four now fail when they find nothing: canonical per-line sby task
conditionals with local paths, pipefail + no continue-on-error + FAIL
fails the step, -g2012 -DSIMULATION + exit 1, lint exit 1, synth-readiness
bails on NOT READY. The expected honest red on lint has a named cause: a
live gen-verilog regression (#2240) that the warning-gate absorbed within
40 minutes of the 32/32 claim.

Closes #2239.
…umulative part-select

state.flags.empty emitted 'state[96 +: 4]_empty' -- the ExprFieldAccess
branch matched identifier, index and call bases but not a field-access
base, so the chain fell through to name-flattening and glued an
identifier fragment onto a part-select (fifo.v, 6 sites, invalid
Verilog live on master; absorbed for 40 minutes by the old warning-only
lint gate). The chain now resolves to a single cumulative part-select:
state[96 +: 1] for flags.empty, state[97 +: 1] for flags.full. Signed
fields keep the $signed() wrap on rvalue reads. M5 performed.

Negative controls: zero glued sites in regenerated fifo.v; yosys parses
it; the full 32-module smoke set lints 32/32 with the repo's own flags.

Closes #2240.
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PR Dashboard

Generated at: 2026-08-19 20:10:08 UTC

Summary

Status Count
Total Open PRs 27
PRs with Failing Checks 9
PRs with All Checks Green 18
READY 9
FAILING 9
PENDING 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=375b2f88cc2f != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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PR Dashboard

Generated at: 2026-08-19 20:19:28 UTC

Summary

Status Count
Total Open PRs 27
PRs with Failing Checks 9
PRs with All Checks Green 18
READY 9
FAILING 9
PENDING 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=375b2f88cc2f != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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This notebook contains session context, decisions, and artifacts for this work.

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gHashTag merged commit d1b9231 into master Aug 19, 2026
26 of 31 checks passed
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gen-verilog: nested struct field after part-select emits glued identifier — fifo.v is invalid Verilog on master

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