gHashTag · gHashTag · Aug 18, 2026 · Aug 18, 2026
@@ -94,7 +94,7 @@
     "Retr": "retracted"
   },
   "cross_repo_consumers": [
-    "gHashTag/tt-trinity-gamma -- RTL for GF4..GF256 (frozen silicon for GF16)",
+    "gHashTag/tt-trinity-gamma -- RTL for GF4..GF256 (frozen tape-out design for GF16)",
     "gHashTag/tt-trinity-corona -- ROM records for all 80 formats; GF cluster routed via D2D to Gamma",
     "gHashTag/goldenfloat-preprint -- arXiv:2606.05017 (cs.AR, live 2026-06-03)",
     "gHashTag/arith2027-goldenfloat -- ARITH 2027 submission",

@@ -153,11 +153,11 @@
     "issue": 129,
     "method": "Mean of ((x - roundtrip(x)) / x)^2 over 512 log-spaced samples between 1e-3 and 3e4 (float32 domain)",
     "nmse": {
-      "GF16_proxy_same_as_ieee_binary16": 4.3990737594875413e-8,
-      "IEEE_bfloat16": 2.6256710851419654e-6,
-      "IEEE_binary16": 4.3990737594875413e-8
+      "GF16_proxy_same_as_ieee_binary16": 4.3990737594875413e-08,
+      "IEEE_bfloat16": 2.6256710851419654e-06,
+      "IEEE_binary16": 4.3990737594875413e-08
     },
-    "note": "Synthetic roundtrip only. `gf16_vectors.json` uses the same IEEE binary16 decode as a GF16 stand-in — not trained-model NMSE.",
+    "note": "Synthetic roundtrip only. `gf16_vectors.json` uses the same IEEE binary16 decode as a GF16 stand-in \u2014 not trained-model NMSE.",
     "samples": 512,
     "x_range": [
       0.001,
@@ -279,7 +279,8 @@
           "speedup_vs_fp32": 2.0
         }
       ],
-      "samples": 10000
+      "samples": 10000,
+      "validity": "INVALID \u2014 model untrained: every format at accuracy 0.1187 / loss 2.3631, against chance 0.1000 and ln(10)=2.3026. Identical scores across formats mean the scenario does not measure the format. Do not cite."
     },
     {
       "description": "Error in representing sacred constants",

@@ -1,3 +1,17 @@
+# NOW -- the withdrawal gate was green because it was blind (2026-08-18)
+
+Last updated: 2026-08-18
+
+## tools: widen the gate that shipped under-scoped, and clear what it then found (Closes #2180)
+
+- **The gate reported OK on 975 documents and could not see the files that mattered.** It scanned `.md`/`.tex`/`.rst` only, so `specs/numeric/formats_catalog.t27:228` -- the canonical CATALOG row for `gf16`, the one that feeds the published dataset -- still carried `FPGA 35/35 at 323 MHz Artix-7`, as did `docs/metrics/numeric_formats_83_metrics.csv:12` and `specs/igla/coder/benchmark.t27:670,677`. A gate that is green because it is under-scoped is the same failure it was built to kill
+- **The withdrawn list was too narrow too.** It held `323 MHz` but not `330 MHz` or `322 MHz`, which are the same `chain[19]` ring-oscillator net read on designs whose claimed sizes differ by 62x -- which is exactly why they agree to 2.5%. `docs/arxiv-submission/trinity-gf16.tex:317-318` still shipped both, and the whole `Max Freq` column is now gone rather than one row blanked
+- Scope is now `.md .tex .rst .t27 .csv .json`, minus `conformance/vectors/`; **4435 documents scanned**, 4.5x the first version
+- **`97.67 % MNIST MLP, 0.00 % accuracy gap vs f32` is withdrawn.** Nothing in the tree produces it. The only MNIST run present, `conformance/gf_family_bench.json`, has **every format at accuracy 0.1187 and loss 2.3631** -- chance for ten classes is 0.1000 and ln(10) is 2.3026, so the model is untrained, and one format scores 0.098, below chance. Every format scoring identically to four decimals is itself the tell that the scenario measures nothing about the format. The scenario is marked INVALID in place rather than deleted
+- **`GF16 -- VERIFIED + FROZEN SILICON` is withdrawn.** `STATUS.md:33` defines SILICON as a physical die received with written bring-up, asserted only on direct device evidence; `STATUS.md:112` states there is to be no SILICON claim anywhere in t27. No die has been received. Four other uses of "frozen silicon" meant the frozen tape-out design, not a received die, and are disambiguated to say so rather than deleted -- the phrase was ambiguous, not false
+- **`fpga/HARDWARE_SSOT.md:1192` is flagged, not corrected.** It reports `Fmax 322 MHz` for a 70-LUT design -- the same value as the withdrawn reading on a 40,350-LUT design. That invariance is the tell, but this design's own clocking has not been re-checked, so the line is marked UNVERIFIED rather than asserted wrong. The baseline is keyed on line text, so removing the marker re-opens the gate
+- Two of the six survey reports were themselves partly stale, written against the tree before the morning's repair landed. Verified every finding against the current tree before acting on it
+
 # NOW -- 323 MHz was a ring oscillator, and a gate now says so (2026-08-18)
 
 Last updated: 2026-08-18

@@ -59,7 +59,7 @@ These four columns are mathematically exact and independently re-derived.
 | GF10  | 1+3+6   | 10   | 3                  | 7                  | 0.500 | 0.118 | Conj | [`gf10.t27`](../specs/numeric/gf10.t27) ‡ |
 | GF12  | 1+4+7   | 12   | 7                  | 15                 | 0.571 | 0.047 | Verified | [`gf12.t27`](../specs/numeric/gf12.t27) |
 | GF14  | 1+5+8   | 14   | 15                 | 31                 | 0.625 | 0.007 | Conj | [`gf14.t27`](../specs/numeric/gf14.t27) ‡ |
-| **GF16 (primary, frozen silicon)** | **1+6+9** | **16** | **31** | **63** | **0.667** | **0.049** | **Verified** | [`gf16.t27`](../specs/numeric/gf16.t27) |
+| **GF16 (primary, frozen tape-out design)** | **1+6+9** | **16** | **31** | **63** | **0.667** | **0.049** | **Verified** | [`gf16.t27`](../specs/numeric/gf16.t27) |
 | GF20  | 1+7+12  | 20   | 63                 | 127                | 0.583 | 0.035 | Verified | [`gf20.t27`](../specs/numeric/gf20.t27) |
 | GF24  | 1+9+14  | 24   | 255                | 511                | 0.643 | 0.025 | Verified | [`gf24.t27`](../specs/numeric/gf24.t27) |
 | GF32  | 1+12+19 | 32   | 2047               | 4095               | 0.632 | 0.014 | Verified | [`gf32.t27`](../specs/numeric/gf32.t27) |
@@ -219,11 +219,20 @@ The whitepaper's latest family table matches the canonical splits above.
 
 ## 6. Implementation status (claim discipline)
 
-- **GF16 — VERIFIED + FROZEN SILICON.** Production Rust (`trios-trainer-igla`) +
+- **GF16 — Verified (spec, codegen, RTL, FPGA testbench).** Production Rust (`trios-trainer-igla`) +
   C codegen ([`../gen/c/numeric/gf16.c`](../gen/c/numeric/gf16.c)) + RTL
   ([`tt-trinity-gamma/src/gf16_v2_mul.v`](../../tt-trinity-gamma/src/gf16_v2_mul.v)
   and `gf16_v2_add.v`); 35/35 FPGA testbench on Artix-7 (no operating frequency claimed — the 323 MHz figure is withdrawn, see docs/nona-03-manifest/RESEARCH_CLAIMS.md); benchmarked
-  (97.67% MNIST MLP, 0.00% accuracy gap vs f32); fabricated in TTSKY26b TT4913 Gamma.
+  against the fp32 reference on synthetic round-trip. **An MNIST figure of "97.67 %,
+  0.00 % accuracy gap vs f32" stood here and is withdrawn**: nothing in the tree
+  produces it, and the only MNIST run present
+  (`conformance/gf_family_bench.json`) has every format at accuracy 0.1187 with
+  loss 2.3631 — chance is 0.1000 and ln(10) is 2.3026, so the model is untrained.
+  Every format scoring identically to four decimals is itself the tell that the
+  scenario measures nothing about the format; one format scores 0.098, below
+  chance. Submitted to the TTSKY26b TT4913 Gamma shuttle; **no die has been
+  received**, and `STATUS.md` reserves SILICON for a physical die with written
+  bring-up and forbids the claim in this repository at all.
 - **GF4/8/12/20/24/32 — Verified.** Spec + Verilog RTL in `tt-trinity-gamma/src/`.
 - **GF64 — Verified.** Spec ([`gf64.t27`](../specs/numeric/gf64.t27), #916) +
   Verilog RTL in gamma; C codegen pending.
@@ -253,7 +262,7 @@ GF64=1+22+41 (should be 1+24+39), GF96=1+33+62 (should be 1+36+59),
 GF128=1+44+83 (should be 1+49+78), GF256=1+88+167 (should be 1+97+158). Corona
 is a registry chip; the on-die arithmetic for GF formats lives in Gamma
 (per `tt-trinity-corona/docs/goldenfloat_ladder_crossreference.md`), and
-Gamma's frozen silicon implements 1+6+9 for GF16. The CATALOG bug is tracked
+Gamma's frozen tape-out design implements 1+6+9 for GF16. The CATALOG bug is tracked
 in [`gHashTag/claim-audit-lab` CASE-09](https://github.com/gHashTag/claim-audit-lab).
 
 ## 7. Measured comparison (IGLA RACE v2 format sweep)

@@ -309,20 +309,20 @@ \subsubsection{4.2 Resource Utilization}\label{resource-utilization}
 {\def\LTcaptype{none} % do not increment counter
 \begin{longtable}[]{@{}lllll@{}}
 \toprule\noalign{}
-Design & LUTs & DSP48E1 & Max Freq & Tests \\
+Design & LUTs & DSP48E1 & Tests \\
 \midrule\noalign{}
 \endhead
 \bottomrule\noalign{}
 \endlastfoot
-GF16 mul & \textasciitilde650 & 1 & 330 MHz & 13/13 \\
-GF16 dot4 & 2,605 & 4 & 322 MHz & 6/6 \\
-GF16 matmul 4x4 & 40,350 & 64 & --- & 35/35 \\
+GF16 mul & \textasciitilde650 & 1 & 13/13 \\
+GF16 dot4 & 2,605 & 4 & 6/6 \\
+GF16 matmul 4x4 & 40,350 & 64 & 35/35 \\
 \end{longtable}
 }
 
 \subsubsection{4.3 Timing}\label{timing}
 
-All designs pass timing at 100 MHz with positive slack:
+Resource figures are \texttt{yosys stat} on the DUT. They are \textbf{not} from the placed wrapper that produced the bitstream: that wrapper feeds the DUT literal constants, so the arithmetic is constant-folded out and its synthesised design module holds 55 cells and no DSP48E1. A \texttt{Max Freq} column stood here and is withdrawn --- all three of its entries came off the same ring-oscillator net:
 
 \begin{verbatim}
 [withdrawn: this clock is a ring-oscillator probe, not a GF16 path]

@@ -9,7 +9,7 @@ gf8_bfp,GF8-BFP (block FP atop GF8),8,1/3/4,3,1.5,1.8,0.132,GoldenFloat,experime
 gf10,GoldenFloat GF10 (10-bit),10,1/3/6,3,2.1,1.8,,GoldenFloat,self,Experimental,Trinity GoldenFloat,расширенный диапазон GF-семейства,bitexact,8,0,0,specs/numeric/gf10.t27
 gf12,GF12,12,1/4/7,7,2.4,4.2,0.047,GoldenFloat,self,Verified,this work; L0/F3,mid-range / audio,bitexact,8,0,0,BENCH-007 (specs/numeric/gf12.t27)
 gf14,GoldenFloat GF14 (14-bit),14,1/5/8,15,2.7,9.0,,GoldenFloat,self,Experimental,Trinity GoldenFloat,расширенный диапазон GF-семейства,bitexact_selfconsistent,,0,0,specs/numeric/gf14.t27
-gf16,GF16,16,1/6/9,31,3.0,18.7,0.049,GoldenFloat,self,Verified,this work; PHI_BIAS=60; FPGA 35/35 at 323 MHz Artix-7,training and inference (production),bitexact,,0,0,specs/numeric/gf16.t27; zenodo 10.5281/zenodo.19227877 (HW archive)
+gf16,GF16,16,1/6/9,31,3.0,18.7,0.049,GoldenFloat,self,Verified,this work; PHI_BIAS=60; FPGA 35/35 on Artix-7 (no frequency claimed; 323 MHz withdrawn),training and inference (production),bitexact,,0,0,specs/numeric/gf16.t27; zenodo 10.5281/zenodo.19227877 (HW archive)
 gf_lns_hybrid,GF + LNS hybrid (dual-space),16,1/6/9,31,3.0,18.7,0.049,GoldenFloat,experimental,Experimental,"this work; mul in log-space, accumulate Lucas-closed",OPEN R&D: dual-space arithmetic,bitexact,8,0,0,section12.5
 gf20,GF20,20,1/7/12,63,3.9,37.9,0.035,GoldenFloat,self,Experimental,this work; 17-squared empirical PHI_BIAS=289,high-precision edge,bitexact,8,0,0,specs/numeric/gf20.t27 (spec only)
 gf24,GF24,24,1/9/14,255,4.5,153.5,0.025,GoldenFloat,self,Experimental,this work; L15 PHI_BIAS=1364,server inference,bitexact,8,0,0,specs/numeric/gf24.t27 (spec only)

@@ -1189,7 +1189,10 @@ xc7frames2bit --frm_file m.frames --output_file m.bit \
 dlc10 sram m.bit         # => STAT 0x401079FC, DONE=HIGH (golden), CRC_ERROR=0
 ```
 
-Result: 70 LUTs, Fmax 322 MHz, `.bit` 3 825 964 B, `STAT=0x401079FC` (matches the
+Result: 70 LUTs, Fmax 322 MHz **[UNVERIFIED — shares its value with the withdrawn
+323/322/330 MHz ring-oscillator readings; this design's own clocking has not been
+re-checked, see RESEARCH_CLAIMS.md Retraction 2026-08-18]**, `.bit` 3 825 964 B,
+`STAT=0x401079FC` (matches the
 known-good golden value).
 
 **Correctness verified (2026-05-31, iverilog 13):** all four bench files

@@ -667,14 +667,15 @@ pub fn cktformalizer_competitor() -> CompetitorScore {
 
 /// goldenfloat_competitor() -> CompetitorScore
 /// GoldenFloat (arXiv:2606.05017v1): Phi-derived floating-point format family.
-/// RTL generator, GF16 passes 35/35 tests at 323 MHz on Xilinx Artix-7.
+/// RTL generator, GF16 passes 35/35 tests on Xilinx Artix-7. The 323 MHz figure
+/// once quoted here is withdrawn (ring-oscillator probe; RESEARCH_CLAIMS.md).
 pub fn goldenfloat_competitor() -> CompetitorScore {
     return CompetitorScore {
         name: "GoldenFloat",
         pass_at_1: 0.0,
         pass_at_5: 0.0,
         pass_at_10: 0.0,
-        benchmark: "Phi-derived FP16 RTL at 323 MHz Artix-7",
+        benchmark: "Phi-derived FP16 RTL on Artix-7 (no frequency claimed)",
     };
 }
 

@@ -225,7 +225,7 @@ module FormatsCatalog {
   // CATALOG: id=gf12 name="GF12" bits=12 s=1 e=4 m=7 bias=7 phi_distance=0.047 storage=u16 cluster=GoldenFloat status=Verified standard="this work; L0/F3" use_case="mid-range / audio" gf_relation=self source="BENCH-007 (specs/numeric/gf12.t27)"
   fn gf12() -> str { return "gf12"; }
 
-  // CATALOG: id=gf16 name="GF16" bits=16 s=1 e=6 m=9 bias=31 phi_distance=0.049 storage=u16 cluster=GoldenFloat status=Verified standard="this work; PHI_BIAS=60; FPGA 35/35 at 323 MHz Artix-7" use_case="training and inference (production)" gf_relation=self source="specs/numeric/gf16.t27; zenodo 10.5281/zenodo.19227877 (HW archive)"
+  // CATALOG: id=gf16 name="GF16" bits=16 s=1 e=6 m=9 bias=31 phi_distance=0.049 storage=u16 cluster=GoldenFloat status=Verified standard="this work; PHI_BIAS=60; FPGA 35/35 on Artix-7 (no frequency claimed; 323 MHz withdrawn, see RESEARCH_CLAIMS.md)" use_case="training and inference (production)" gf_relation=self source="specs/numeric/gf16.t27; zenodo 10.5281/zenodo.19227877 (HW archive)"
   fn gf16() -> str { return "gf16"; }
 
   // CATALOG: id=gf20 name="GF20" bits=20 s=1 e=7 m=12 bias=63 phi_distance=0.035 storage=u32 cluster=GoldenFloat status=Experimental standard="this work; 17-squared empirical PHI_BIAS=289" use_case="high-precision edge" gf_relation=self source="specs/numeric/gf20.t27 (spec only)"

@@ -41,7 +41,7 @@ module GoldenFloatFamily {
     //
     // Status (v1.2):
     //   - Verified arithmetic (rule produces exact widths): 17/17.
-    //   - Frozen silicon anchor: GF16 = 1+6+9, bias = 31
+    //   - Frozen tape-out anchor: GF16 = 1+6+9, bias = 31
     //     (tt-trinity-gamma/src/gf16_v2_mul.v).
     //   - Whether the ladder is BETTER than an equally-tuned non-phi
     //     family (posit / OCP-MX / takum / LNS) stays [Open conjecture].

@@ -13,7 +13,13 @@
 The lesson generalises past this one number: a correction recorded in notes does
 not propagate to documents, and nothing was checking. So this checks.
 
-  live document      any tracked .md / .tex / .rst, minus the exclusions below
+  live document      any tracked .md / .tex / .rst / .t27 / .csv / .json, minus the
+                     exclusions below. The machine-readable types are in scope
+                     because the first version was not, and was green while
+                     specs/numeric/formats_catalog.t27 -- the canonical CATALOG row
+                     that feeds the published dataset -- still carried the number.
+                     A gate that is green because it is under-scoped is the same
+                     failure it was built to kill.
   exclusions         the claims registry itself (it must state what it withdrew),
                      dated history under docs/reports/ (a record of what was
                      believed then is not a live claim), and this gate's own data
@@ -40,10 +46,11 @@
 ROOT = pathlib.Path(__file__).resolve().parent.parent
 REGISTRY = ROOT / "tools/withdrawn.txt"
 BASELINE = ROOT / "tools/withdrawn_live_baseline.txt"
-SUFFIXES = {".md", ".tex", ".rst"}
+SUFFIXES = {".md", ".tex", ".rst", ".t27", ".csv", ".json"}
 EXCLUDE_PREFIXES = (
     "docs/nona-03-manifest/RESEARCH_CLAIMS.md",   # must state what it withdrew
     "docs/reports/",                              # dated history, not live claims
+    "conformance/vectors/",                       # numeric test data, not prose
     "tools/withdrawn.txt",
     "tools/withdrawn_live_baseline.txt",
     "tools/check_withdrawn_live.py",

@@ -9,3 +9,12 @@
 323(\.[0-9]+)?\s*MHz | ring-oscillator toggle rate, not a GF16 path | RESEARCH_CLAIMS.md Retraction 2026-08-18
 41\.2\s*GOPS         | derived from the withdrawn 323 MHz            | RESEARCH_CLAIMS.md Retraction 2026-08-18
 322M\s*matmuls/sec   | derived from the withdrawn 323 MHz            | RESEARCH_CLAIMS.md Retraction 2026-08-18
+
+# Added 2026-08-18 after the first version of this gate ran green while three
+# machine-readable files still carried the number. All three frequencies below
+# came off the same chain[19] ring-oscillator net, on designs whose claimed sizes
+# differ by 62x -- which is why they agree to 2.5%.
+330\s*MHz            | same ring-oscillator net as 323 MHz (GF16 mul row)  | RESEARCH_CLAIMS.md Retraction 2026-08-18
+322\s*MHz            | same ring-oscillator net as 323 MHz (GF16 dot4 row) | RESEARCH_CLAIMS.md Retraction 2026-08-18
+97\.67\s*%?\s*MNIST  | no artifact produces it; the only MNIST run is untrained | RESEARCH_CLAIMS.md Retraction 2026-08-18
+FROZEN\s+SILICON     | STATUS.md reserves SILICON for a received die, and forbids it in t27 | STATUS.md:33,112
@@ -1,10 +1,22 @@
 # Occurrences that are text ABOUT a withdrawal, not a live claim.
 # Keyed path | pattern | sha1(line)[:12] -- editing the line re-opens the gate,
 # which is what we want for append-only documents like docs/NOW.md.
+docs/NOW.md | 322\s*MHz | 21a54d698621
+docs/NOW.md | 322\s*MHz | e01a7fd68109
 docs/NOW.md | 323(\.[0-9]+)?\s*MHz | 18f57dc20b45
 docs/NOW.md | 323(\.[0-9]+)?\s*MHz | 700c6d6aca11
 docs/NOW.md | 323(\.[0-9]+)?\s*MHz | ce84017e739b
+docs/NOW.md | 323(\.[0-9]+)?\s*MHz | e01a7fd68109
+docs/NOW.md | 323(\.[0-9]+)?\s*MHz | f81569f4b61c
+docs/NOW.md | 330\s*MHz | e01a7fd68109
+docs/NOW.md | 97\.67\s*%?\s*MNIST | 776e9a8ea0df
+docs/NOW.md | FROZEN\s+SILICON | f4b106440c67
 docs/NUMERIC_FORMATS_SSOT.md | 323(\.[0-9]+)?\s*MHz | bbc2adf030a9
 docs/arxiv-trinity-gf16-draft.md | 322M\s*matmuls/sec | 1026a341042f
 docs/arxiv-trinity-gf16-draft.md | 323(\.[0-9]+)?\s*MHz | 6daf60f68b57
 docs/arxiv-trinity-gf16-draft.md | 41\.2\s*GOPS | 546e04c73288
+docs/metrics/numeric_formats_83_metrics.csv | 323(\.[0-9]+)?\s*MHz | 708d88e59591
+fpga/HARDWARE_SSOT.md | 322\s*MHz | 65210d3dc292
+fpga/HARDWARE_SSOT.md | 330\s*MHz | 558353792f10
+specs/igla/coder/benchmark.t27 | 323(\.[0-9]+)?\s*MHz | da656d208e0a
+specs/numeric/formats_catalog.t27 | 323(\.[0-9]+)?\s*MHz | c83b3c67224c