Unbreak FPGA CI and correct two unbacked hardware claims

.github/workflows/fpga-build.yml

@@ -324,8 +324,8 @@ jobs:
         run: |
           if [ ! -f ~/.local/bin/nextpnr-xilinx ]; then
             cd ~
-            git clone https://github.com/YosysHQ/nextpnr.git -b nextpnr-0.8
-            cd nextpnr
+            git clone https://github.com/gatecat/nextpnr-xilinx.git
+            cd nextpnr-xilinx
             mkdir build && cd build
             cmake .. -DARCH=xilinx -DUSE_OPENMP=OFF
             make -j4

README.md

@@ -57,8 +57,8 @@ Discoverability mirror of the numeric corpus. GitHub remains the primary source
 | Compiler | `t27c parse` | GREEN | 170+ specs parse |
 | Compiler | `t27c gen-verilog` | GREEN | 5/5 FPGA modules synthesize |
 | Compiler | `t27c seal` | GREEN | 170+ seals in `.trinity/seals/` |
-| FPGA | Yosys synthesis | GREEN | 5/5 modules pass synth_xilinx |
-| FPGA | E2E bitstream | GREEN | Yosys→nextpnr→prjxray→.bit (zero Vivado) |
+| FPGA | Yosys synthesis | RED | `fpga-synthesis` CI job failing; last green 2026-04-14. Local `gen-verilog` smoke still passes 5/5 |
+| FPGA | E2E bitstream | RED | Yosys→nextpnr→prjxray→.bit never validated in CI: `fpga-build.yml` is 36 success / 842 failure / 3 cancelled over 881 runs, and `fpga-bitstream` is skipped behind `needs: fpga-synthesis` |
 | FPGA | Board profiles | GREEN | QMTECH XC7A100T (minimal+full), Arty A7 |
 | FPGA | `--profile` flag | GREEN | `--profile minimal|full` in fpga-build |
 | Pins | Pins IR | GREEN | `specs/pins/ir.t27` — conflict detection invariants |
@@ -67,7 +67,7 @@ Discoverability mirror of the numeric corpus. GitHub remains the primary source
 | CI | Seal coverage | GREEN | All specs sealed |
 | CI | Schema validation | GREEN | Conformance vectors validated |
 | CI | FPGA smoke | GREEN | Verilog gen in CI |
-| CI | FPGA bitstream artifact | GREEN | .bit uploaded per PR (7-day retention) |
+| CI | FPGA bitstream artifact | RED | No .bit uploaded since 2026-04-14 — job skipped behind failing `fpga-synthesis` |
 | TRI | PHI LOOP CLI | GREEN | `cli/tri/` standalone binary |
 | TRI | MCP server | GREEN | `cli/tri-mcp/` — 10 tools over JSON-RPC |
 | Spec | Phase 3 (shell/tools/file) | YELLOW | 6/8 parse; 2 file specs have parser issue (#388) |

bootstrap/src/main.rs

@@ -4934,7 +4934,7 @@ endmodule
         fs::write(
             &synth_script,
             format!(
-                "read_verilog {files}\nhierarchy -check -top {top}\nproc; opt; fsm; opt; memory; opt\nsynth_xilinx -top {top}\nwrite_json {json}\nstat\n",
+                "read_verilog -sv -DSIMULATION {files}\nhierarchy -check -top {top}\nproc; opt; fsm; opt; memory; opt\nsynth_xilinx -top {top}\nwrite_json {json}\nstat\n",
                 files = verilog_files,
                 top = top,
                 json = synth_json.display(),
@@ -4959,7 +4959,7 @@ endmodule
         fs::write(
             &synth_script,
             format!(
-                "read_verilog {files}\nhierarchy -check -top {top}\nproc; opt; fsm; opt; memory; opt\nsynth_xilinx -top {top}\nwrite_json {json}\nstat\n",
+                "read_verilog -sv -DSIMULATION {files}\nhierarchy -check -top {top}\nproc; opt; fsm; opt; memory; opt\nsynth_xilinx -top {top}\nwrite_json {json}\nstat\n",
                 files = verilog_files,
                 top = top,
                 json = synth_json.display(),

docs/arxiv-submission/trinity-gf16.tex

@@ -293,7 +293,7 @@ \subsubsection{4.1 Platform}\label{platform}
 \begin{itemize}
 \tightlist
 \item
-  \textbf{FPGA:} QMTECH XC7A100T-1FGG676C (Artix-7, 126,800 LUTs, 240
+  \textbf{FPGA:} QMTECH XC7A100T-1FGG676C (Artix-7, 63,400 LUTs, 240
   DSP48E1)
 \item
   \textbf{Toolchain:} openXC7 (Yosys 0.62 + nextpnr-xilinx)

docs/arxiv-trinity-gf16-draft.md

@@ -113,7 +113,7 @@ C[i][j] = dot4(A[i][0:3], B[0:3][j])
 
 ### 4.1 Platform
 
-- **FPGA:** QMTECH XC7A100T-1FGG676C (Artix-7, 126,800 LUTs, 240 DSP48E1)
+- **FPGA:** QMTECH XC7A100T-1FGG676C (Artix-7, 63,400 LUTs, 240 DSP48E1)
 - **Toolchain:** openXC7 (Yosys 0.62 + nextpnr-xilinx)
 - **Clock:** 20-stage ring oscillator (onboard M21 crystal non-functional)
 - **Programming:** XVC via ESP32 (192.168.1.30:2542)

specs/numeric/formats_catalog.t27

@@ -225,7 +225,7 @@ module FormatsCatalog {
   // CATALOG: id=gf12 name="GF12" bits=12 s=1 e=4 m=7 bias=7 phi_distance=0.047 storage=u16 cluster=GoldenFloat status=Verified standard="this work; L0/F3" use_case="mid-range / audio" gf_relation=self source="BENCH-007 (specs/numeric/gf12.t27)"
   fn gf12() -> str { return "gf12"; }
 
-  // CATALOG: id=gf16 name="GF16" bits=16 s=1 e=6 m=9 bias=31 phi_distance=0.049 storage=u16 cluster=GoldenFloat status=Verified standard="this work; PHI_BIAS=60; FPGA 35/35 at 323 MHz Artix-7" use_case="training and inference (production)" gf_relation=self source="specs/numeric/gf16.t27; zenodo 10.5281/zenodo.19227877 (HW archive)"
+  // CATALOG: id=gf16 name="GF16" bits=16 s=1 e=6 m=9 bias=31 phi_distance=0.049 storage=u16 cluster=GoldenFloat status=Verified standard="this work; PHI_BIAS=60" use_case="training and inference (production)" gf_relation=self source="specs/numeric/gf16.t27"
   fn gf16() -> str { return "gf16"; }
 
   // CATALOG: id=gf20 name="GF20" bits=20 s=1 e=7 m=12 bias=63 phi_distance=0.035 storage=u32 cluster=GoldenFloat status=Experimental standard="this work; 17-squared empirical PHI_BIAS=289" use_case="high-precision edge" gf_relation=self source="specs/numeric/gf20.t27 (spec only)"