Unbreak FPGA CI and correct two unbacked hardware claims

[dmitrii-f-t27]

Four independent fixes, all small.

1. fpga-synthesis has been red since 2026-04-14. Both writers of synth.ys in bootstrap/src/main.rs (:4937 Docker branch, :4962 local-yosys branch) emit read_verilog {files} with the Verilog-2005 frontend, while the backend deliberately emits SystemVerilog static casts (compiler.rs:5068). Yosys therefore fails with Static cast is only supported in SystemVerilog mode on build/fpga/generated/uart.v. Both now read read_verilog -sv -DSIMULATION {files}, matching the invocation that already works at suite.rs:859.

That fpga-synthesis-arty passes today is not a counter-example: --minimal narrows the yosys input to {top}.v, which carries no test blocks.

2. fpga-bitstream has never succeeded once. .github/workflows/fpga-build.yml:327 clones upstream YosysHQ/nextpnr and configures -DARCH=xilinx, but upstream nextpnr has no xilinx architecture — nextpnr-xilinx is a separate fork. CMake rejects the arch and the job exits 1. Now clones gatecat/nextpnr-xilinx.

⚠️ This will not turn the job green on its own. The Create chipdb symlink step writes a 1 MB /dev/zero placeholder, and real nextpnr-xilinx will reject it. Building the chipdb from prjxray-db is a larger change and is deliberately not in this PR.

3. README claimed GREEN for three red rows. Measured from the API: fpga-build.yml has 881 runs — 36 success, 842 failure, 3 cancelled; last success 2026-04-14; the fpga-bitstream job is skipped behind needs: fpga-synthesis. Those three rows now read RED with the last-green date. The gen-verilog smoke rows are left GREEN — that path uses the correct invocation and does pass.

4. Two unbacked hardware figures.

specs/numeric/formats_catalog.t27:228 cited zenodo 10.5281/zenodo.19227877 as its hardware archive. That DOI resolves to Trinity B007: VSA Operations for Ternary Computing v5.0 — resource type Software, one 2.0 kB file, no FPGA frequency and no design. The 323 MHz figure and the Zenodo citation are removed; source now points at specs/numeric/gf16.t27. The 35/35 claim goes with them: the only 35/35 in this repo is Icarus and cocotb, i.e. simulation, not an FPGA run.

docs/arxiv-submission/trinity-gf16.tex:296 and docs/arxiv-trinity-gf16-draft.md:116 give the XC7A100T LUT count as 126,800. That is the part's flip-flop count; its LUT count is 63,400. Corrected. Note this makes the design's occupancy look better, not worse: 40,350/63,400 = 63.6%.

Not in this PR, flagged for you:

• specs/igla/coder/benchmark.t27:670 and :677 carry the same 35/35 at 323 MHz. That file faithfully quotes arXiv:2606.05017, so editing it before a v4 correction would desynchronise it from its own source.
• The spiOverJtag_xc7a100tfgg676.bit rename (the file is an FTG256 bitstream; the real FGG676 build is parked under .v2) involves binaries and a .gz regeneration.