Fix custom-symbol port directions and trace endpoints

[MustafaMulla29]

Summary

• honor explicit direction values on ports inside React and Circuit JSON custom symbols
• derive side_of_component from the same explicit direction instead of fallback schematic-box metadata
• reconnect solver-generated traces to the authoritative custom-symbol port center when the port lies on or outside the symbol boundary
• preserve intentional interior custom-symbol ports, which should remain projected to the symbol edge
• cover the behavior with the exact imported DMT6007LFG_7 reproduction and schematic snapshots

Root cause

Port direction

A chip can retain fallback schematic-box placement metadata while rendering a custom symbol. Port rendering previously allowed that fallback side to override the custom symbol port's explicit direction. The emitted schematic_port could therefore face the wrong way, causing net labels such as GATE to be placed inward.

Disconnected trace endpoint

The schematic solver can project a custom-symbol boundary port onto its routing-box edge. Core already reconnects solver-adjusted endpoints to authoritative schematic_port centers for text-expanded components, but custom symbols without text-expanded bounds were excluded. This left a visible gap between the SOURCE trace and the imported MOSFET's S3 port.

The endpoint reconciliation now also recognizes genuine React and Circuit JSON custom symbols. It remains restricted to ports on or outside the normal symbol boundary, so it does not draw traces through symbols that intentionally declare interior ports.

Validation

• exact imported DMT6007LFG_7 regression with and without traces/net labels
• custom-symbol interior-port regression
• ordinary RP2040, ATmega, schematic-section, and cross-sheet snapshot regressions
• bunx tsc --noEmit
• all 10 CI test shards, format check, type check, and smoke test pass

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Project	Deployment	Actions	Updated (UTC)
tscircuit-core-benchmarks	Ready	Preview	Aug 20, 2026 7:33am