[codex] Detect different-net via pad clearance

[seveibar]

Summary

• extend checkDifferentNetViaSpacing to check both drill-hole and copper-pad clearance
• evaluate each different-net via pair once and emit only the most relevant error
• preserve the existing drill-hole error when both manufacturing constraints fail
• turn the reproduction from PR [codex] Add overlapping via pad short reproduction #213 into a passing regression with a visual DRC snapshot

Why

The existing different-net via spacing check measures drill-hole edge clearance. Two vias can therefore satisfy the drill rule while their larger copper annuli overlap or violate the board's pad-edge clearance. This stacked change folds the shared-layer annulus check into the same via-pair loop, checks it against min_pad_edge_to_pad_edge_clearance, and reports a standard pcb_pad_pad_clearance_error when the drill rule itself passes.

Stacked on #213; review that reproduction first.

Verification

• bun test — 178 passed
• bun run build
• bunx tsc --noEmit
• focused regression and visual SVG snapshot updated

[tscircuitbot]

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Thank you for your contribution! 🎉

PR Rating: ⭐⭐
Impact: Minor

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