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Add copper pour overlap DRC check - #190

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zkasuran:feat/copper-pour-overlap-check
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Add copper pour overlap DRC check#190
zkasuran wants to merge 1 commit into
tscircuit:mainfrom
zkasuran:feat/copper-pour-overlap-check

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@zkasuran

@zkasuran zkasuran commented Aug 8, 2026

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Closes #189

What this does

Adds checkCopperPourOverlap, a DRC check that flags copper pours on the same layer that belong to different nets and whose filled regions overlap. Overlapping fills on different nets are physically the same copper, so the two nets are shorted together.

This is the detection for the short reported in tscircuit/core#3074, where two default full-board pours on one layer each fill the whole board and overlap with no diagnostic. The pour geometry is produced by the solver in core; this change only inspects the resulting pcb_copper_pour records, so it is additive and does not touch the solver.

How it works

  • Net membership is resolved through the connectivity map (getFullConnectivityMapFromCircuitJson), so two pours that name different nets which are electrically tied read as the same net and are left alone, matching checkDifferentNetViaSpacing.
  • Only pours on the same layer with a known net on both sides are compared.
  • Each pour is turned into its filled region (rect, polygon or brep outer ring with inner rings as holes) and the pair is flagged when the boolean intersection area is above a small threshold. Regions that only touch along an edge intersect to zero area and are left alone, so abutting or disjoint planes stay clean.
  • One pcb_trace_error is emitted per overlapping pair, deduped by pour id pair, carrying the overlap center so shouldDrawErrors renders it.
  • Wired into runAllRoutingChecks next to the other net-aware checks.

Tests

  • check-copper-pour-overlap.test.ts: overlap on different nets flags one error; same-net, different-layer, disjoint and electrically-tied nets each produce no error.
  • copper-pour-overlap-drc-snapshot.test.ts: renders the error over the two overlapping pours with convertCircuitJsonToPcbSvg({ shouldDrawErrors: true }).

Verified locally

  • bun test (147 pass, 0 fail)
  • bunx tsc --noEmit clean
  • bun run format:check clean
  • bunx @tscircuit/dependency-check passes
  • bun run build succeeds

AI assistance

AI assistance (Claude, Anthropic) was used in developing this change. The design, review and verification were done by the author. Verified locally before submitting: bun test, bunx tsc --noEmit, bun run format:check, dependency-check and build all pass.

Detect copper pours on the same layer that belong to different nets and
whose filled regions overlap. Overlapping fills on different nets are
physically connected copper so the two nets are shorted together. The
check resolves net membership through the connectivity map so electrically
tied nets are left alone, and it is wired into runAllChecks.

Detection for the short reported in tscircuit/core#3074.
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New DRC check: flag overlapping copper pours on different nets

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