fix: flag different-net via copper overlap, not just drill-hole spacing

[zkasuran]

Closes #183

checkDifferentNetViaSpacing measures the gap between two vias hole-edge-to-hole-edge, so it only ever sees the drill holes and never the copper annular ring (outer_diameter). Two vias on different nets whose copper overlaps into a short pass DRC clean as long as their drill holes stay min_via_hole_edge_to_via_hole_edge_clearance apart.

Repro

// outer_diameter 0.6mm, hole 0.3mm, centers 0.5mm apart
// copper edge gap = 0.5 - 0.3 - 0.3 = -0.1mm (rings overlap, a short)
// hole edge gap   = 0.5 - 0.15 - 0.15 = 0.2mm (clears the 0.1mm hole spacing)
checkDifferentNetViaSpacing([viaA, viaB]) // [] on main

The change

Keep the existing hole-edge (drill) check and add a copper-edge check: compute the gap between the outer_diameter rings and flag it against min_pad_edge_to_pad_edge_clearance, the same electrical clearance a different-net copper pad uses. When the drill holes are the ones too close the error still reports the hole gap, so existing behavior and fixtures are untouched; the new path only catches the copper overlap the drill check missed. This matches checkViaTraceClearance, which already treats a via's extent as its outer_diameter.

Verification

• New test copper-ring-overlap-short.test.ts: [] on main, one pcb_via_clearance_error after.
• Full check suite green (142 pass), including the existing different-net via tests (no regression, no snapshot changes).
• bunx tsc --noEmit clean, biome format clean.

Disclosure

AI assistance (Claude, Anthropic) was used in developing this change. Verified locally before submitting: the new test, the full bun test suite (142 pass), bunx tsc --noEmit and biome format.

[seveibar]

Can you add a visual repro before comitting the fix? Use an svg snapshot

[zkasuran]

Done. Added copper-ring-overlap-short.test.ts with an SVG snapshot repro that renders the two different-net vias with overlapping copper and the clearance error drawn. Full suite stays green (142 pass). Pushed.