SteffenReith / J1Sc Star 90 Code Issues Pull requests A reimplementation of a tiny stack CPU cpu fpga vhdl forth verilog hdl j1-cpu spinalhdl Updated Dec 8, 2023 Scala
rob-ng15 / Silice-Playground Star 37 Code Issues Pull requests Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice fpga forth risc-v rv32i j1-cpu de10nano rv32 rv32im rv32imc ulx3s fomu Updated Jul 2, 2023 C
pbing / J1 Star 20 Code Issues Pull requests Forth CPU J1 in SystemVerilog systemverilog j1-cpu forth-cpu Updated Apr 29, 2017 Forth
ThorKn / J1-forth Star 18 Code Issues Pull requests Forth for the J1-CPU fpga aes forth hdl spinal j1-cpu spinalhdl j1sc j1 Updated Mar 13, 2017 Forth
LightHouseSoftware / j1_cpu Star 2 Code Issues Pull requests Implementation of the J1 Forth CPU in D programming language dlang forth j1-cpu Updated Jun 11, 2018 D
PetrGlad / iceFUN Star 2 Code Issues Pull requests Extensions to the original iceFUN ice40 examples, includes ADC reading, integrated J1 CPU, improved LED matrix control with PWM brigtness setting. fpga ice40 j1-cpu Updated Apr 17, 2021 Verilog
roycrippen / j1-cpu Star 2 Code Issues Pull requests J1 CPU emulator written in Rust. emulator rust forth j1-cpu j1 Updated Sep 25, 2020 Rust