Pinned Loading

1. LDO_DESIGN_7nm_FinFET LDO_DESIGN_7nm_FinFET Public

   Custom LDO design in a 7nm FinFET process: two-stage OTA error amplifier driving a PMOS pass transistor, with feedforward capacitor compensation. Achieves 72.75° phase margin, 15.18 dB gain margin,…

   2

2. TSMC7nm-TwoStage-OpAmp TSMC7nm-TwoStage-OpAmp Public

   Fully characterized two-stage OTA designed and simulated in Cadence Virtuoso using Spectre. All analyses were run at the schematic level. Desgined to function as an error amplifier for LDO.

3. Dynamic-Memory-Configuration-and-Reconfiguration-on-FPGA Dynamic-Memory-Configuration-and-Reconfiguration-on-FPGA Public

   This project implements a fully hardware-based dynamic DDR memory allocator in SystemVerilog. The allocator divides DDR memory into independent regions — one per hardware component — each backed b…

   SystemVerilog 2

4. JLFET-vs-CIGAAFET JLFET-vs-CIGAAFET Public

   Sentaurus TCAD simulation study of 8 nm nanowire Gate-All-Around FETs in Core-Insulator GAAFET (CIGAAFET) configuration along with JUNCTIONLESS FET. Course project for BEVD206L Semiconductor Devic…

   3 1

5. bjt-thermal-sensing-cadence bjt-thermal-sensing-cadence Public

   BJT-based PTAT thermal sensing circuit with adaptive biasing — designed and simulated in Cadence Virtuoso

   1

6. ecg-music-emotion-hrv ecg-music-emotion-hrv Public

   FILTER TO ANALYSE ECG SIGNALS VIA WEARABLES to avoid loss in signal information

   Python 2