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1. riscv-5stage-pipeline-cache riscv-5stage-pipeline-cache Public

   A synthesizable 5-stage RV32I RISC-V pipelined processor in pure Verilog-2001. Features EX/MEM data forwarding, hazard detection (load-use & branch stalls), a 2-level (L1/L2) cache hierarchy interf…

   Verilog 2

2. UART UART Public

   Serial data transfer is a core building block in digital systems, and the best way to understand it deeply is to build it yourself! I recently designed and verified a full-duplex UART (Universal As…

   Verilog 1

3. CMOS-Circuit-Design-and-Simulation-Using-SKY130 CMOS-Circuit-Design-and-Simulation-Using-SKY130 Public

   CMOS circuit design and SPICE simulation study covering NMOS behavior, inverter VTC, noise margins, and robustness analysis.

   2

4. H-Bridge-Multilevel-Inverter-with-SPWM H-Bridge-Multilevel-Inverter-with-SPWM Public

   Designed and evaluated an SPWM-based cascaded H-bridge multilevel inverter in MATLAB/Simulink to enhance power quality through harmonic reduction.

   2

5. Active-and-Passive-Filter-Design Active-and-Passive-Filter-Design Public

   This project designs and implements active and passive analog filters using op-amps and passive components. Its main objective is to improve signal quality by passing desired frequency bands while …

   1

6. ARM7TDMI-Worksheet ARM7TDMI-Worksheet Public

   Assembly 1