[sw/test] Add upstream RISC-V scalar ISA tests (rv32u*) as RTL ctests

[Smephite]

What

Adds the upstream riscv-software-src/riscv-tests scalar suites (rv32ui, rv32um, rv32uf, rv32ud) to the build as RTL ctests, alongside the existing vector .c tests. This gives Spatz's scalar/FP core (Snitch + the FPU sequencer path) direct ISA-level coverage it previously lacked.

How

• sw/riscvTests/RiscvIsaTests.cmake — FetchContent pulls riscv-tests at a pinned tag, builds each test against the stock env/p (its own _start, trap handler, tohost pass/fail), and registers it as an RTL ctest via ${SNITCH_SIMULATOR}. No snRuntime linkage. The per-suite <ext>_sc_tests list from each upstream Makefrag is parsed (rather than globbing) to honour upstream's own selection.
• sw/riscvTests/patches/move-fcsr-wpri.patch — masks Spatz's non-standard fmode bits (fcsr[9:8]) in upstream move.S, which otherwise leak into the WPRI region the test reads back.
• sw/riscvTests/CMakeLists.txt — includes the above.
• Unimplemented capabilities are gated, not silently skipped: fdiv/ma_data are marked WILL_FAIL behind RVTESTS_HAS_DIVSQRT / RVTESTS_HAS_MISALIGNED (both OFF by default), so they build and run but don't red the suite.

Baseline on current main

63/71 pass. The 8 failures are all real scalar-FP bugs in main, which this harness now surfaces:

Failing test (case)	Bug	Fix
rv32ud-p-ldst (6)	flw not NaN-boxed	#109
rv32uf-p-fclass (2), rv32uf/ud-p-fcmp (10)	unboxed narrow FP operand misread	#109
rv32uf/ud-p-fcvt_w (2)	scalar fcvt.w.d/s INT width	#110
rv32ud-p-fcvt (5), rv32ud-p-fmadd (2)	fp32→fp64 special widening / FP64 rs3 width	—

With the corresponding FP fixes applied, the suite goes 71/71 (verified locally). Landing this harness first gives those fix PRs a concrete regression target.

Notes

• fdiv stays WILL_FAIL until scalar HW divsqrt lands; flip RVTESTS_HAS_DIVSQRT=ON then.
• Self-contained: no changes to RTL or runtime.