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Spatz ope - #102

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boboloiono wants to merge 11 commits into
pulp-platform:mainfrom
boboloiono:spatz-ope
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Spatz ope#102
boboloiono wants to merge 11 commits into
pulp-platform:mainfrom
boboloiono:spatz-ope

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@boboloiono

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@bowwwang bowwwang left a comment

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Thanks for your work. We will try to provide a bi-weekly code review so that we can align on the progress, and provide help promptly.

At this point the issue is quite common, especially on the coding style. Good thing is that we still have time to fix this, but you need deep clean up in your current code based.

Comment thread sw/riscvTests/isa/rv64uv/vtmmu_tvv.c Outdated
// A row2 = [ 9, 10, 11, 12]
VLOAD_8(v12, 9,10,11,12, 0,0,0,0, 0,0,0,0, 0,0,0,0);
// A row3 = [13, 14, 15, 16]
VLOAD_8(v14,13,14,15,16, 0,0,0,0, 0,0,0,0, 0,0,0,0);

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Just a side reminder, adding MACRO functions in a test is not a good practice, since people need to trace where this MACRO was defined and come back and forth.

Try to just write kernel with asm instructions

Comment thread sw/riscvTests/isa/rv64uv/vtmmu_tvv.c Outdated
TEST_CASE1();

EXIT_CHECK();
} No newline at end of file

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also here why the main is not defines seperately?


#ifndef VTMMS_ALT_INSN
#define VTMMS_ALT_INSN "vtmms.alt.tvv"
#endif

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please do not use MACRO like this

VLE8("v23", _b1 + 3*(int)N); \
VTMM_GROUP(INSN); \
} \
} while (0)

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For example here, I understand it may seems to be cleaner, but still try to align with the code convention. You can refer to the existing tests

#undef VLSE8
#undef ZERO_4TILES
#undef LOAD_4TILES_I32
#undef STORE_4TILES_I32 No newline at end of file

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this is interesting. I never see this #undef before. Any reason using it?

@@ -0,0 +1,18 @@
// Copyright 2024 ETH Zurich and University of Bologna.

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Remember to update the timestamp to 2026. welcome to the new world :)

boboloiono and others added 11 commits June 27, 2026 20:07
- but PyTorch running on CPU doesn't support float(Half)
- add a vme test temporily inside riscvTests
- modify LLVM_INSTALL_DIR in iis-env.sh
- 21 VME instruction can generate the assembly correctly and pass the ISA test
- auto-generate both FP and INT config data & data headers
- add CMakeLists to include FP and INT functional tests main.c
- remove macros and handler and use inline assembly
- support only fp32*fp32 gemm for the application as now
- add XVEM flag
- offload VME instructions from snitch to spatz decoder
- add VME decoding in spatz_decoder
- add MTYPE csr in spatz pkg, add alt_fmt in VTYPE csr in rvv pkg
- add tile config param in spatz pkg
- add mset* FSM in spatz_controller
- add ope/ module files: opope_accumulator, opope_fma, opope_pkg, spatz_ope
- integrate OPE + VENTAGLIO into spatz.sv (tile interface, shared VRF arbitration)
- integrate tile interface into spatz_doublebw_vlsu.sv (VTLE/VTSE)
- add VMCFG/proc_mcsr, mtype_q/tn_q CSRs, OPE case in ex_issue to spatz_controller
- [doublebw_vlsu] repack the tile mem store mode
- [controller] add OPE scoreboard
- [spatz_ope] add two FSM states
- [FPU_sequencer] register VTLE, VTSE instr
- [decoder] temporily move VTLE, VTSE riscv-instr case before vector load/store instr because VTLE32 and VLX64_V use the same bit encoding
- [Bender.yml] add OPE src files (fma, accumulator)
- switch spatz_cluster default config to doublebw.dram.hjson
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2 participants