Add support for Digilent Basys3 board - #130
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This exposes JTAG through a PMOD, which is unfortunate.
Replace dmi_jtag_tap with dmi_bscane_tap so RISC-V debug uses the FPGA's built-in config JTAG instead of four PMOD JA I/Os. External JTAG ports are removed from croc_xilinx for TARGET_BASYS3; internal dummy wires satisfy croc_soc's port list (ignored by dmi_bscane_tap). XDC constraints for PMOD JA and the CLOCK_DEDICATED_ROUTE workaround are dropped. An OpenOCD script is added that connects via the on-board FTDI adapter and remaps DTMCS/DMI to USER3/USER4 IR codes (0x22/0x23).
…targets add_sources.basys3.tcl is autogenerated by bender; without the 'xilinx' and 'bscane' targets the riscv-dbg Bender.yml condition all(xilinx,bscane) evaluates false and dmi_jtag_tap.sv is selected, overwriting the BSCANE2 intent on every --flist/--all run. Pass both extra targets for basys3 so the generated file consistently picks dmi_bscane_tap.sv. Also restore the current add_sources.basys3.tcl to match.
…p Debugger 0.12.0+dev-04404-geb01c632a (2025-10-09-10:08)
phsauter
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Two smaller points, otherwise it looks good.
| CONFIG.CLK_OUT1_PORT {clk_20} \ | ||
| CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {20.000} \ | ||
| CONFIG.CLKIN1_JITTER_PS {50.0} \ | ||
| CONFIG.MMCM_CLKFBOUT_MULT_F {6.000} \ | ||
| CONFIG.MMCM_CLKIN1_PERIOD {5.000} \ | ||
| CONFIG.MMCM_CLKOUT1_DIVIDE {60} \ |
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I think this works but is wrong.
The primary frequency is now 100 MHz and the requested output is 20MHz, then it uses a multiplier of 6 and division of 60. So it will produce a 10MHz clock just fine but the CLKIN1_PERIOD is defined as 5ns, which does not match the 100MHz.
I would consider splitting it completely by board similar to how Cheshire does it: https://github.com/pulp-platform/cheshire/blob/main/target/xilinx/scripts/impl_ip.tcl#L20
and then generating/verifying it with the actual clkwiz.
| # Basys3 uses BSCANE2 for JTAG: pass 'xilinx' and 'bscane' so that | ||
| # riscv-dbg selects dmi_bscane_tap.sv instead of dmi_jtag_tap.sv. | ||
| local extra_targets="" | ||
| if [ "$TARGET" = "basys3" ]; then | ||
| extra_targets="-t xilinx -t bscane" | ||
| fi |
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Instead of this we could use a rather new bender feature documented here. and directly say 'if this target is passed, pass another target to a dependency'.
riscv-dbg:
git: "https://github.com/pulp-platform/riscv-dbg.git"
rev: "verilator-phsauter"
pass_targets:
- { target: basys3, pass: bscane }
So this would automatically pass bscane to riscv-dbg if the target basys3 is defined.
I think it would be a cleaner solution and if people manually use bender, it won't break.
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This pull request adds support for building and running the CROC SoC on the Digilent Basys3 FPGA board (https://digilent.com/reference/programmable-logic/basys-3/reference-manual), in addition to the previously supported Genesys2 board. The changes include updates to the build system, hardware description, and scripts to handle board-specific differences such as clocking, reset, and JTAG/debug interfaces. The scripts and hardware now automatically adapt to the selected target board, and a new OpenOCD script is provided for debugging via the Basys3's internal JTAG.
Basys3 FPGA support
Bender.yml,run_xilinx.sh,add_sources.basys3.tcl,common.tcl). [1] [2] [3] [4] [5]run_xilinx.shto accept a--targetargument for board selection, generate board-specific file lists, and create separate build directories/logs per target. [1] [2] [3] [4] [5]Hardware description updates
croc_xilinx.svto support both Genesys2 and Basys3: added board-specificdefines, conditional differential/single-ended clock buffer instantiation, and conditional JTAG/BSCANE2 debug logic. [1] [2] [3] [4] [5] [6] [7] [8]Board-specific scripts and configuration
xilinx/scripts/add_sources.basys3.tclfor Basys3 Vivado project sources, and updatedxilinx/scripts/common.tclwith Basys3 part numbers and configuration. [1] [2]impl_ip.tcl).Debug and development tools
xilinx/scripts/openocd.basys3.tcl, an OpenOCD script for debugging the SoC on Basys3 using the FPGA's internal JTAG (BSCANE2), eliminating the need for external JTAG cables.Other improvements
run_xilinx.shfor better maintainability, including improved help output and removal of hardcoded directory creation. [1] [2]These changes make it straightforward to build, implement, and debug the CROC SoC on both Genesys2 and Basys3 boards, with board-specific configuration handled automatically.