Ndh/speed up spi nor

[nathanaelhuffman]

I've stacked this for now on the axi-pipes branch, but will rebase this against main once axi-pipes lands. This allows review of just this change.

Here we increase the SPI nor frequency to 62.5MHz (up from ~20MHz). This required some link layer optimization and the addition of some timing constraints for this. Simulation coverage has also increased.

At least when benchmark over usb, this basically make 0 difference as the usb transfers dominate the performance there.

Given what we know about flash and the system performance, it is unclear whether this will speed anything up in product but it gets the FPGA shift speed out of the way for any future performance investigation. There is probably additional optimization to be had around queueing up more data or other interface changes here should any hubris benchmarking suggest additional optimization opportunity.

Change summary:
Speed up sclk 20.83 MHz → 62.5 MHz (clk/6 → clk/2 off clk_125m) .
The register map untouched, so hubris code requires no changes.
Sclk rate and sample point are new generics on spi_nor_top.

A number of bugs that were not evident at the slower clock frequency were fixed as they were evident at faster speeds:

• opcode serialized in the transaction's data mode during cs_assert. This would result in an incorrect opcode sent to the device.
• OE followed the byte-aligned mode, resulting in IO3 re-driven into the part on a quad read turnaround.
• output teardown at end of write, resulting in corrupting the last sample edge at the flash part.
• sclk_running conflated with in_tx_phases resulted in trailing clocks during cs_deassert. Erase and write-enable could be silently discarded in this case.
• io mode taken from the registered state at the reload edge resulted in the first quad data byte shifted by 1 not 4, so we lost the sentinel in the register and the transaction never terminated.

Structural Changes:
TX launches on the sclk falling edge itself; byte and io mode are prefetched together; RX sampling moved to a placed point (rx_sample_taps, half-clk steps) fed by rising/falling capture flops; every pin-facing flop duplicated with no internal fanout and packed into its IOB to close timing. (IOB packing reduces 12–13 ns of routing to ~3.3 ns).

This has been tested in hardware on a cosmo with the following somewhat adhoc tests via humility:

host flash slot: Flash0
test region:     0x400000 .. 0x410000

[id] read JEDEC ID + unique ID
    mfr=0xef type=0x40 capacity=0x21
    uid=ea626c4097221b35ea626c710313313600
    PASS (1.5s)

[status] read status register, check WIP clear
    status = 0x00
    PASS (1.4s)

[erase] sector erase leaves every byte of the sector 0xFF
    PASS (5.7s)

[page_program] program a page and read it back
    PASS (5.5s)

[partial_page] sub-page write of a non-multiple-of-4 length
    PASS (5.7s)

[multi_page] program four consecutive pages, verify the whole sector
    PASS (8.3s)

[odd_lengths] reads of awkward lengths at awkward offsets
    8 length/offset combinations verified (last one crosses a page boundary)
    PASS (15.2s)

[bit_clear] reprogramming without erase only clears bits
    PASS (7.3s)

[ff_write_noop] writing all-0xFF is a documented no-op
    PASS (5.8s)

[erase_after_write] erase clears a programmed sector, and is idempotent
    PASS (7.4s)

[neighbor_isolation] operations do not disturb the adjacent sector
    PASS (5.5s)

[diffwrite] -D programs a full sector; a second -D finds no delta
    second pass reported no delta
    PASS (12.9s)

[bad_address] out-of-slot access is rejected, not silently wrapped
    rejected as expected
    PASS (1.4s)

[sector0_guard] sector 0 is refused without --write-sector0
    refused as expected
    PASS (1.1s)

[throughput] time a full-sector -D write and a full-sector hash pass
    hash (read) pass: 1.46s -> 43.9 KiB/s including invocation overhead
    write pass:       7.40s -> 8.7 KiB/s (erase + program)
    PASS (10.5s)

[Aaron-Hartwig]

Some small notes you can take or leave.