feat(awg): add burst to awg - #367
Conversation
|
Preview deployment for your docs. Learn more about Mintlify Previews.
💡 Tip: Enable Workflows to automatically generate PRs for you. |
|
Claude finished @LizzyC-115's task in 4m 26s —— View job Review complete
Overview: Solid addition — burst mirrors the existing modulation feature's shape closely (optional
Inline comment posted on |
| _check_channel(channel) | ||
| return self._visa.query(f":SOUR{channel}:BURS:STAT?").strip() == "ON" | ||
|
|
||
| def set_burst_trigger(self, channel: int, source: BurstTriggerSource) -> None: |
There was a problem hiding this comment.
Every other burst property has a set/get pair (enable/state, delay, type, polarity, ncycles, period) — matching the PR description's stated goal of "set/get pairs for ... trigger". There's no get_burst_trigger/readback for trigger source here or in awg.py. If :BURS:TRIG:SOUR? is queryable on this instrument, worth adding for symmetry; if not queryable, worth a one-line note explaining the omission.
There was a problem hiding this comment.
Updated the naming conventions to match the other functions with set_gate_/get_gate_
af4b3b0 to
2fddb27
Compare
|
|
||
| def burst_enable(self, channel: int, enable: bool) -> None: | ||
| _check_channel(channel) | ||
| self._write_checked(f":SOUR{channel}:BURS:STAT {'ON' if enable else 'OFF'}") |
There was a problem hiding this comment.
Note that commands with _write_checked use a helper function that called _check_errors()
Greptile SummaryAdds burst-mode support to the Rigol DG1022Z AWG driver and exposes it through the public AWG abstraction.
Confidence Score: 5/5The PR appears safe to merge, with no concrete blocking or independently actionable non-blocking issues identified. The new public APIs follow existing AWG packaging and locking patterns, the Rigol implementation checks device errors and mode restrictions, and the added tests cover the principal command, parsing, validation, and hardware paths. Important Files Changed
|
|
Claude finished @LizzyC-115's task in 3m 18s —— View job Code review complete
Overview: The remaining gaps from the earlier review pass have been addressed well — Two items, both minor:
No other correctness, convention, or scope issues found. Base-class contract, |
| self._check_errors() | ||
| return result | ||
|
|
||
| def set_ncycles(self, channel: int, n_cycles: int) -> None: |
There was a problem hiding this comment.
Naming asymmetry remains here: set_ncycles → get_burst_ncycles. The set_gate_polarity/get_gate_polarity pair was already fixed for symmetry per the earlier review thread, but this pair (and its AWGDriverBase/InstroAWG counterparts in awg.py) wasn't — worth the same treatment (get_ncycles or set_burst_ncycles) before this API stabilizes.
Summary
Add burst funtionality into the Rigol DG1022Z AWG driver. Using the same structure as modulation, we use
set/getpairs for enable, delay, period, trigger, type, polarity, and ncycles.Type of change
fix)feat)feat!/fix!)refactor)docs)chore)Verification
Tests
Checklist
feat(driver): add support for Keysight E36300)