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Pre-release custom FlexRIO code for use with LabVIEW FPGA HDL Tools

What is this? - Core Concepts

  • This repository contains examples of customized FlexRIO FPGA devices
  • These examples use the LabVIEW FPGA HDL Tools to manage dependencies, create Vivado projects and integrate custom HDL with LabVIEW
  • These examples depends on a number of other repositorires that contain FlexRIO and shared HDL source code. These dependencies are installed (cloned) by the LabVIEW FPGA HDL Tools.
  • You can perform workflows for customizing LabVIEW FPGA targets with HDL
    • Use HDL-only and Vivado to build a bitfile and communicate with it from the NI-RIO driver on a host PC
    • Use HDL to make a custom LabVIEW FPGA target that can be extended in LabVIEW FPGA and use the standard LabVIEW FPGA bitfile generation workflow
    • Use LabVIEW FPGA to make a top-level VI that is exported as a netlist and brought into your custom HDL to build in Vivado
  • You can communicate between the NI-RIO driver on a host PC and custom HDL directly using
    • Registers
    • DMA FIFOs
  • All of this is pre-release and not supported by NI
    • Use the Issues and Discussions sections in this repository to collaborate with the developers and other lead users


Supported Devices

FlexRIO Co-Processor Modules

Device
PXIe-7903
PXIe-7903-DDR1280
PXIe-7911
PXIe-7912
PXIe-7915

FlexRIO High-Speed Serial Modules

Device Baseboard
PXIe-6593 KU35 PXIe-7981
PXIe-6593 KU40 PXIe-7982
PXIe-6593 KU60 PXIe-7985
PXIe-6594 PXIe-7986

FlexRIO Multifunction IO Modules

Device Baseboard
PXIe-7890 PXIe-7994
PXIe-7891 PXIe-7994

For the High-Speed Serial and Multifunction IO Modules, start with the Custom folder for the baseboard module.

Customizing IO Module Devices

Modules with integrated IO use an IO Module ID (also called Terminal Block ID or TbId in the VHDL) to ensure that the LabVIEW FPGA CLIP node is compatible with the device. When customizing the device in VHDL, use this IO Module ID to ensure that the integrated IO is enabled.

IO Module IDs

Device IO Module ID
PXIe-7903 0x10937AEC
PXIe-7903-DDR1280 0x10937AEC
PXIe-7911 none
PXIe-7912 none
PXIe-7915 none
PXIe-6593 KU35 0x109379F9
PXIe-6593 KU40 0x109379F9
PXIe-6593 KU60 0x109379F9
PXIe-6594 0x109379FC
PXIe-7890 0x10937AA7
PXIe-7891 0x10937AA8

System Setup

Follow these steps to setup your machine to use the LabVIEW FPGA HDL Tools with this flexrio-custom GitHub repository

Prerequisite Software

Use NI Package Manager to install the following software:

  • LabVIEW 2023 (or newer)
  • LabVIEW FPGA 2023 (or newer)
  • LabVIEW FPGA Compilation tool for Vivado 2021.1
  • FlexRIO 2026 Q3 (or newer)

Install the following 3rd party software:

1) Clone this repo

In a dev folder (e.g. c:\dev\github) clone the repo:

git clone https://github.com/ni/flexrio-custom

List tags for all the releases:

git tag

Checkout the repo at a specific tag/version:

git checkout tags/26.x.y

(main branch may be unstable; we recommend checking out the latest version that does not have "dev" in the name)

2) Go to the custom target folder

cd C:\dev\github\flexrio-custom\targets\pxie-7903custom

All command line operations are performed from within a target folder

3) Set up the Python environment

nisetup

This creates a virtual environment, installs the correct version of the LabVIEW FPGA HDL Tools, and activates the environment.

Important: You must run nisetup every time you open a new command prompt. The virtual environment is only active for the current terminal session. You will see (flexrio-custom) in your command prompt when the environment is active.

4) Run nihdl --help to see the list of available commands

nihdl --help

5) Install dependencies

nihdl install-deps

This will download the dependencies specified in the dependencies.toml file found here:

C:\dev\github\flexrio-custom\dependencies.toml


That's it! Your computer is setup to use the LabVIEW FPGA HDL Tools to make custom FlexRIO FPGA devices


Getting Started

Step-by-step exercises for building bitfiles, customizing a target, and migrating a socketed CLIP have moved to docs/GettingStarted.md.

Repo Folder Hierarchy

  • Root repo folder
    • .github - CI workflows and repo automation
    • deps - checked-out GitHub dependencies installed by nihdl install-deps
    • docs - repository documentation
    • targets - FPGA target projects (one folder per supported device)
      • common - shared files used across the target projects
      • pxie-7903custom - example custom PXIe-7903 device (consider this to be the "Hello World" example)
        • nihdlsettings.py - tool configuration (Python-based target settings)
        • nisetup.bat - runs the repo-root setup script to activate the Python environment
        • lvFpgaTarget - LabVIEW FPGA target plugin source files
        • blankLvWindowNetlist - placeholder LabVIEW window netlist content
        • rtl-lvfpga - target HDL sources
        • xdc - timing constraints
        • VivadoProject - Vivado project files (ignored in .gitignore)
        • ModelSimProject - ModelSim simulation project files (ignored in .gitignore)
        • objects - generated outputs from HDL tools (ignored in .gitignore)
        • docs - target-specific documentation and examples
        • vivadoprojectsources.txt - source list used for Vivado project generation
        • vivadoprojectexclude.txt - files excluded from the generated Vivado project
        • modelsimprojectsources.txt - source list used for ModelSim project generation
      • pxie-7903aurora - example of migrating the Aurora CLIP to make a custom Aurora PXIe-7903 device
      • pxie-7xxxCustom - additional custom device examples
    • tests / test-targets - automated tests and test targets
    • dependencies.toml - dependency version specification for nihdl install-deps and Python tool versions
    • nisetup.bat - sets up a Python virtual environment and installs dependencies
    • nisetup.py - Python script that creates the venv and installs packages from dependencies.toml
    • CONTRIBUTING.md, SECURITY.md, LICENSE - project meta files

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