Research Engineer | Aspiring PhD & Master Candidate in AI & Hardware Security

I'm a systems engineer and researcher working at the intersection of Computer Architecture, Hardware Security, and Applied AI — bridging low-level silicon microarchitecture with high-level agentic and neural reasoning systems.

My background combines open-source hardware fundamentals with industry experience building agentic systems. I focus on engineering secure intelligent hardware, auditing microarchitectural threat surfaces, and exploring ML vulnerabilities at the physical layer.

• AI & Hardware Security Intersection: Machine learning attacks on physical/hardware primitives (e.g., Physical Unclonable Function modeling), automated hardware backdoor/Trojan verification, and agentic code auditing frameworks.
• Computer Architecture & Silicon Workflows: RTL design (Verilog), processor design (RISC-V ISA), structural control unit FSMs, pipeline hazard mitigations, logic optimization, and memory-safe systems programming (Rust).
• Applied Cryptography & Network Defense: Secure-by-design cryptographic system deployment (authenticated symmetric encryption combined with asymmetric key wrapping models), topological threat graphing, and CVSS-driven risk derivation.

• Autonomous AI Agent System: Co-architected and implemented a fully autonomous agent framework driven by Anthropic's Claude APIs. Engineered the orchestration layer to allow the agent to capture abstract user specifications, automatically generate code architectures, run native test suites, execute self-debugging loops, resolve environment dependencies, schedule internal tasks, and handle continuous multi-cloud deployment.
• Scalable Infrastructure & DevOps: Built and optimized robust relational data infrastructure using PostgreSQL deployed on AWS RDS. Containerized microservice clusters via Docker to enforce cross-environment parity. Developed deep workflow automation routines using n8n deployed across hybrid AWS and Azure enterprise boundaries.

• Designed an offensive hardware evaluation suite focused on modeling Arbiter Physical Unclonable Functions (PUFs).
• Demonstrated the fragility of silicon delay-based security primitives by collecting Challenge-Response Pairs (CRPs) and utilizing mathematical machine learning models to simulate, map, and successfully clone the hardware fingerprint with high predictive accuracy.

• Built a clean-room implementation of a 32-bit RISC-V processor conforming to the RV32I ISA specification from scratch using Verilog.
• Implemented the underlying execution architecture including Arithmetic Logic Units (ALUs), structural control unit Finite State Machines (FSMs), and register file access logic.
• Analyzed pipeline data hazards and microarchitectural bottlenecks — developing foundational knowledge on where physical side-channels and microarchitectural leaks manifest.

• Engineered a high-performance, memory-safe implementation of the Longest Prefix Match (LPM) routing algorithm using Rust.
• Leveraged Rust's zero-cost abstractions, robust type system, and concurrency models to build an efficient packet-forwarding simulation layer optimized for network systems.

• Logic Circuits Simulator: Programmed a discrete event logic simulator capable of simulating logical gate propagation delays and boolean algebra processing.
• Digital Clock: Designed and implemented a digital time-tracking logic architecture, mapping register increments to timing matrices.

• Contributed to an advanced Natural Language Processing (NLP) framework built to test and expand cognitive temporal logic in Transformers.
• Worked on dataset preprocessing pipelines, fine-tuning methodologies, and chronology-focused evaluation structures to stress-test large language models on tracking data consistency, causal chains, and timeline reconstruction.

• Compiled an academic repository of deep dives, implementations, and derivations covering core machine learning algorithms from scratch. Includes regression, categorization, mathematical validation frameworks, and optimization mechanics.

• Developed a highly structured, educational python-based security toolkit simulating modern file-encryption frameworks.
• Constructed a pristine hybrid cryptographic orchestration layer utilizing AES-256-GCM for authenticated file stream data encryption wrapped by RSA-4096 (OAEP + SHA-256) keys for secure asymmetric management.
• Fully structured as an immutable, safe-by-design package with zero-extortion, localized environments, and rigorous validation tests.

• Modeled security landscapes by implementing network asset threat structures using graph-theoretic Python libraries (NetworkX, Matplotlib).
• Generated topological network maps to evaluate vulnerability chains, deriving adaptive path weights utilizing dynamic CVSS (Common Vulnerability Scoring System) parameter metrics.
• Authored a professional security disclosure policy (SECURITY.md) outlining vulnerability reporting procedures and structural legal safe harbor constraints.

I am highly interested in discussing PhD opportunities, collaborative research projects, or advanced engineering positions in AI hardware optimization, microarchitectural security, or cryptographic hardware modeling.

• 🌐 LinkedIn: Mohamed Khaled
• 💻 GitHub Profile: @mmohamedkhaled
• 🎓 Academic Email: mohamedabdelfatah572@aucegypt.edu