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LATX, AVX: defer redundant VEX.128 upper-half clears - #437

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luzeng87:avx-deferred-ymmh-zero
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LATX, AVX: defer redundant VEX.128 upper-half clears#437
luzeng87 wants to merge 1 commit into
lat-opensource:masterfrom
luzeng87:avx-deferred-ymmh-zero

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Summary / 变更说明

  • Track VEX.128 destinations whose architectural YMM high halves are known to be zero.
  • Defer redundant LASX high-half clears until a 256-bit operation can observe the state or the TB is about to exit.
  • Materialize pending clears before guest-visible exits so JIT, TU, AOT, and signal state keep x86 semantics.
  • Add a standalone semantic test covering native x86, LAT JIT, cold AOT, and hot AOT execution.

This change does not modify the AOT cache identity or enable LAT --optimize-O2.

Validation / 验证

  • 3A6000-25G, GCC 8.3.0 -O2 -g, LAT --optimize-O1: clean x86_64 build passed.
  • meson test -C build64-pr --suite lat-pr-fast: 24 passed, 0 failed.
  • vex128-ymmh-zero.S: native x86, LAT JIT, cold AOT, and hot AOT all passed; non-empty hot cache was loaded.
  • The stacked GB603 branch containing this commit completed a clean i386 LAT build (407/407 build steps).

Checklist / 检查项

  • I have read CONTRIBUTING.md. / 我已阅读 CONTRIBUTING.md
  • Every commit contains a DCO sign-off (git commit -s). / 每个提交都包含 DCO 签署。
  • I have included relevant build or test results. / 我已提供相关构建和测试结果。

Track VEX.128 destinations whose architectural YMM high halves are known to be zero, and materialize those clears only when a 256-bit operation can observe them or before leaving the TB. This removes repeated LASX clear instructions while preserving signal, JIT, TU, and AOT-visible state.

Add a standalone JIT, cold-AOT, and hot-AOT semantic test for the deferred state.

Signed-off-by: Lu Zeng <luzeng87@gmail.com>
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