LATX: translate AES and VAES encryption rounds directly

[luzeng87]

Summary

• key AOT caches by LATX build identity so incompatible generated code is not reused
• translate AESENC/AESENCLAST and VEX AES rounds directly to IR2 instead of helper calls
• translate 256-bit VAES encryption rounds with LASX and advertise VAES with the AVX path
• invalidate a cached AES table address after loading a complex memory round key, fixing consecutive base+index memory-source rounds
• add AES, VEX-XMM, and VAES-YMM regression programs covering register, memory, aliasing, repeated rounds, JIT, and AOT execution

Bug

convert_mem() may reuse the physical GPR that still contains the cached AES table address. A following AES or VEX-AES instruction then sees the cache tag as valid and reads through the overwritten address. Two consecutive rounds using [base + index * scale] reproduced the failure.

The memory-key loader now clears the table cache tag after emitting the load. The next direct round reloads the table address before using it.

Validation

• clean LoongArch64 build with AVX optimization and AOT enabled: 410/410 targets
• meson test --suite lat-pr-fast --print-errorlogs: 24/24 passed
• native x86 reference: AES, all-byte AESENC, and VEX-XMM guests passed
• LATX JIT: AES, all-byte AESENC, VEX-XMM, and VAES-YMM guests passed
• LATX cold/hot AOT: AES, VEX-XMM, and VAES-YMM guests passed; non-empty caches were 18,643, 19,827, and 14,243 bytes
• Geekbench 7 geekbench_avx2 --workload 101 --no-upload: hot AOT scores 745 and 741 on 3A6000-25g

The 3A6000-25g host does not provide clang, so the x86 assembly guests were built as static binaries on an x86 host and then executed by the final LATX binary. The registered integration runner skips when clang is unavailable.