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🐛 Fix write mask for whole-register write - #190

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mjcaisse-intel merged 2 commits into
intel:mainfrom
elbeno:fix-written-mask
Sep 1, 2026
Merged

🐛 Fix write mask for whole-register write#190
mjcaisse-intel merged 2 commits into
intel:mainfrom
elbeno:fix-written-mask

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@elbeno

@elbeno elbeno commented Aug 31, 2026

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Problem:

  • When some bits in a register are not allocated into fields, writing a value to that register ("reg"_r = value) may incur a read-modify-write, because the mask used is the fields mask, despite the intention to write to the whole register.

Solution:

  • When writing to a path, use the mask for the path rather than the mask aggregated from its known children.

Problem:
- When some bits in a register are not allocated into fields, writing a value to
  that register (`"reg"_r = value`) may incur a read-modify-write, because the
  mask used is the fields mask, despite the intention to write to the whole
  register.

Solution:
- When writing to a path, use the mask for the path rather than the mask
  aggregated from its known children.
Problem:
- There is no test exercising overlapping field writes.

Solution:
- Add a test.
- This is a niche situation, but when fields overlap and are written, the
  ordering of the arguments determines the actual written value.

Example:
```cpp
// given fields:
using F0 = field<"f0", std::uint8_t, 0, 0>;
using F1 = field<"f1", std::uint8_t, 1, 0>;  // contains (overlaps) F0

// when we say
write(grp("r.f0"_f = 1, "r.f1"_f = 0));

// the resulting value is 0b00
// i.e. as-if 1 is written to F0, then 0 is written to F1
// F1 "overwrites" F0

// when we say
write(grp("r.f1"_f = 0, "r.f0"_f = 1));

// the resulting value is 0b01
// i.e. as-if 0 is written to F1, then 1 is written to F0
// F0 "overwrites" F1
```

Note:
- Fields which overlap in a parent-child relationship already provoke a
  compile-time error. i.e. the following is ill-formed:

```cpp
write(grp("r"_r = 0, "r.f0" = 1));
```
@mjcaisse-intel
mjcaisse-intel merged commit 5b99abd into intel:main Sep 1, 2026
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2 participants