docs: reconcile catalog counts, LUT figures and device manifest against their sources - #543
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…st their sources
Each fix takes the value from the file this repo already names as the source for
that quantity; no number here is newly derived except the two recomputed
percentages, which come from counts already in the edited table.
README.md:11 — SW-bitexact 75/83 -> 62/83 strict, with 69/83 as the count
including self-consistent packs, and the two defined. Source:
fpga/CATALOG_MATRIX_83.md:11,27 (strict 62) and :31 (69), restated in
.claude/skills/fpga-synth/SKILL.md:1142 as "~62-69/83".
README.md:13 — compute-HW Tier-E 16 cells -> 30 cells, and the enumeration
corrected to ten GF formats x {ADD, MUL, SUB}. Source:
fpga/CATALOG_MATRIX_83.md:29 ("ADD 10/10 + MUL 10/10 + SUB 10/10");
the ten format names from research/SUBMISSION_CHECKLIST.md:55.
README.md:94 — same fix in prose: the enumeration omitted GF10, GF14 and the
whole SUB family, giving 8 x 2 = 16 instead of 10 x 3 = 30.
README.md:113 — SW-bitexact ceiling restated as above. The "remaining 8" was
derived from 75/83 and no longer holds; dropped rather than replaced, since
the sources give 15 structural packs against a 62 strict / 69 inclusive split
and reconciling them is the owner's call.
fpga/CATALOG_MATRIX_83.md:31 — "Total Tier-E HW: 71/83" replaced by the two axes
stated separately, per the wording the project already prescribed at
research/arxiv_v3_catalog_update.md:191: "~41 decode cells + ~10 compute
cells". 41 counts formats, 30 counts cells, the 83 denominator counts formats,
and the ten GF compute formats are already inside the decode-41 list, so the
sum was a unit error and a double count.
research/arxiv_submission/paper.tex:776 — GF16 parameterized adder 486 -> 491.
README.md:102 — same, 486 -> 491.
research/CATALOG_PAPER_DRAFT.md:329 — same, 486 -> 491.
Source: research/LUT_COMPARISON_MEASURED.md:73,75 — 491 with -flatten, 486
without; the paper's prose (paper.tex:828) states -flatten and already says
491, so the table row was the outlier.
fpga/bitstream/MANIFEST.md:10 — die XC7A200T -> XC7A100T. IDCODE 0x13631093 has
part field 0x3631, which this repo's own fpga/IDCODE.md:14 and its
cross-reference table at :23-24 decode as XC7A100T; 0x3636 is the A200T.
fpga/bitstream/MANIFEST.md:12 — Package FGG484 -> FGG676, per fpga/IDCODE.md:1,26
(the QMTech XC7A100T board is FGG676; FBG484 is the distinct ALINX AX7203).
fpga/bitstream/MANIFEST.md:21-22 — utilisation was computed against XC7A200T
capacity. Recomputed from the counts already in those lines against the
XC7A100T denominators: 83/63,400 = 0.13%, 27/126,800 = 0.02%.
fpga/phiscale/README.md:33 — the "No Fmax / nextpnr-xilinx is not installed"
bullet scoped explicitly to scale_phi and pointed at the ladder logs. This
exact note is named in
research/frontier/WITHDRAWAL_FMAX_UNSOURCED_2026-08-10.md:32-36 as the cause
of a false accusation that the ladder Fmax figures were unsourced; that file
records the note belongs to an earlier design from before the tool was
available. Scoped rather than deleted so the scale_phi caveat survives.
research/lut_comparison.md:97,130,142 — every quoted 118 LUT labelled as
gf16_add_top (deprecated; no denormal/NaN handling) with the conformant 491
alongside, and the Posit16 comparison restated against 491 (~3x, was ~12x
against 118). Sources: README.md:107 and
research/LUT_COMPARISON_MEASURED.md:21,23.
.gitignore:422 — removed the phiscale-specific log rule and added negations for
fpga/phiscale/cs_*.log, fpga/phiscale/cy_*.log, fpga/tnet/ws_*.log and
fpga/tnet/cs_e_*.log, which the blanket *.log at :51 was also swallowing.
These place-and-route logs are the sole evidence for the paper's Fmax column
and git ls-files currently shows zero .log files tracked anywhere. The log
files themselves are NOT in this commit — they are on the maintainer's
machine; this change only makes them committable.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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Each of these is one quantity stated inconsistently across files, corrected to the value its own source gives. Several were already recorded as fixed in
.trinity/experience/, but the fix had reached only one of the files.fpga/CATALOG_MATRIX_83.md:29(README calls it the live SSOT)CATALOG_MATRIX_83.md:11,27,31; already corrected in.claude/skills/fpga-synth/SKILL.md:59gf_adder_paramLUT_COMPARISON_MEASURED.md:75— 486 is the count without-flatten, and the paper states-flattenMANIFEST.md0x13631093→ part0x3631, decoded by this repo's ownfpga/IDCODE.md:14Total Tier-E HW: 71/83 removed. It is a unit error and a double count: 41 counts formats carrying a decode cell, 30 counts cells (10 GF formats × ADD/MUL/SUB), the 83 denominator counts formats, and the ten GF compute formats are already inside the decode-41 list. The two axes are now reported separately and never summed, using the wording already prescribed at
research/arxiv_v3_catalog_update.md§7.6.Withdrawn group claim removed from the paper.
research/arxiv_tnf/tnf_paper.tex:1834still asserted the fixed-vs-tapered gap as 2.4 to 6.4×.WITHDRAWAL_13_GROUPSwithdrew it andDECODER_FULL_OBSsplit the finding by axis: by area the groups overlap (IBM hex32 243 LUT against posit8 214), by frequency the worst fixed field leads the best taper by 1.43×, well outside seed spread. The paper now says that, and names the figure it withdraws.lut_comparison.md: the 118 LUT figure is labelled. The Posit16 costs ~12× headline was computed againstgf16_add_top, whichREADME.md:107already states is deprecated and omits denormal/NaN/parameterization logic. Every 118 is now labelled as such, the conformant 491 is given alongside, and the ratio is restated against 491 (~3×).fpga/phiscale/README.md: the note that caused a false withdrawal is scoped. No Fmax. nextpnr-xilinx is not installed on this machine belongs toscale_phi, from before the tool was available — not to the ladder runs, which do have post-route measurements.WITHDRAWAL_FMAX_UNSOURCED_2026-08-10.mdnames this bullet as cause #2 of a serious false accusation and lists the corrections it applied; this README was not among them. Now scoped explicitly, with a pointer to the logs and to that withdrawal..gitignore: the paper's evidence can now be committed.*.logplus a phiscale rule excluded every place-and-route log, sogit ls-files | grep '\.log$'returns 0 — the 298 + 110 logs that closed the Fmax provenance question are not in the public repo. An outside reader lands exactly where the first (wrong) withdrawal landed. Negations added forfpga/phiscale/cs_*.log,cy_*.log,fpga/tnet/ws_*.log,cs_e_*.log; verified withgit check-ignorethat these are now tracked and other.logfiles are not.