Skip to content

ci(fpga): formal [script] reads with -sv -DSIMULATION - #2258

Merged
gHashTag merged 1 commit into
masterfrom
ci/formal-read-flags
Aug 19, 2026
Merged

ci(fpga): formal [script] reads with -sv -DSIMULATION#2258
gHashTag merged 1 commit into
masterfrom
ci/formal-read-flags

Conversation

@gHashTag

Copy link
Copy Markdown
Owner

Closes #2257. Refs #2239. Formal layer 5: the base yosys step now reads the repo's own dialect. Locally verified flag pair. docs/NOW.md updated.

🤖 Generated with Claude Code

Formal layer 5: with the cwd fix in place sby ran its base yosys step for
the first time in the job's history and died on fifo.v:369 TOK_INITIAL --
without -DSIMULATION the ifndef-guarded bench block (initial statements)
survives into the formal read, and the emitter's SV static casts need -sv;
every other Verilog reader in this repo already applies both flags.
Verified locally: bare 'read_verilog -formal fifo.v' fails, with the flags
it exits 0.

Closes #2257.
@gHashTag
gHashTag enabled auto-merge (squash) August 19, 2026 22:31
@github-actions

Copy link
Copy Markdown
Contributor

📓 NotebookLM Notebook linked to this PR

This notebook contains session context, decisions, and artifacts for this work.

@github-actions

Copy link
Copy Markdown
Contributor

PR Dashboard

Generated at: 2026-08-19 22:31:19 UTC

Summary

Status Count
Total Open PRs 24
PRs with Failing Checks 9
PRs with All Checks Green 15
READY 7
FAILING 9
PENDING 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=375b2f88cc2f != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@gHashTag
gHashTag merged commit 1684af3 into master Aug 19, 2026
18 of 20 checks passed
gHashTag added a commit that referenced this pull request Aug 19, 2026
…#2260)

PR #2258 changed only .sby configs and merged with zero fpga-build runs:
the files the formal job consumes were invisible to its own CI. Both the
push and pull_request path lists now include contrib/formal/** and
conformance/fpga_*.json.

Closes #2259.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

fpga-formal layer 5: sby's yosys reads the .v without -sv -DSIMULATION — bench blocks break the base step

1 participant