ci(fpga): formal [script] reads with -sv -DSIMULATION - #2258
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Formal layer 5: with the cwd fix in place sby ran its base yosys step for the first time in the job's history and died on fifo.v:369 TOK_INITIAL -- without -DSIMULATION the ifndef-guarded bench block (initial statements) survives into the formal read, and the emitter's SV static casts need -sv; every other Verilog reader in this repo already applies both flags. Verified locally: bare 'read_verilog -formal fifo.v' fails, with the flags it exits 0. Closes #2257.
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August 19, 2026 22:31
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Closes #2257. Refs #2239. Formal layer 5: the base yosys step now reads the repo's own dialect. Locally verified flag pair. docs/NOW.md updated.
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