A dead simulator reads as a design that emitted nothing - #2194
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Last site of the class opened in #2187/#2189, and it sits on the load-bearing proof: Verilog == model. verify_emit_bitexact.py:127 took vvp's stdout with no exit-code check. A crashed simulator yields a short Y-list and the next check reports FAIL (2, 2, 1): step count RTL=0 PY=80 which reads as 'the RTL emitted no outputs' -- a design fault. Nothing had been compared. The testbench already said so. It contains initial begin #60000000 $display("TIMEOUT"); $finish; end printing TIMEOUT into the very stdout this script parses, and the script never looked for it. A design that ran out of simulated time is not a design that disagrees with the model, and the two want different fixes. Order is now: vvp's exit code (with the signal number when negative), then the TIMEOUT marker, then the step count -- which states explicitly that vvp exited 0 and printed no TIMEOUT, so a mismatch there is a real disagreement. Verified by shortening the testbench timeout so the branch actually fires, rather than by reading it. Clean tree still exits 0. The class is closed: an AST re-scan leaves two run(...).stdout sites, both git ls-files inside try/except with check=True and an rglob fallback, so a git failure raises and is handled rather than swallowed. A hardcoded #60000000 went into the message on the first pass and was removed on the second -- a literal copied into prose is the drift this cycle has been correcting. Closes #2193 Refs #2189 Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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Last site of the class opened in #2187 / #2189, and it sits on the load-bearing proof: Verilog == model.
tools/verify_emit_bitexact.py:127ran the simulator aswith no exit-code check. A
vvpthat crashes produces a short Y-list, and the next check reportswhich reads as the RTL emitted no outputs — a design fault. Nothing was compared.
And the testbench already says so. It contains
initial begin #60000000 $display("TIMEOUT"); $finish; end— the wordTIMEOUTis printed into the very stdout the script parses, and the script never looked for it. A design that ran out of simulated time is not a design that disagrees with the model, and the two want completely different fixes.Fix: check
vvp's exit code (reporting the signal number when negative), then look for theTIMEOUTmarker, then fall through to the step-count check — which now says explicitly that vvp exited 0 and printed no TIMEOUT, so a count mismatch there is a real disagreement.Verified by shortening the testbench timeout so the branch actually fires:
Clean tree still exits 0 (
ALL SYNTHESIZE).The class is now closed. An AST re-scan leaves two
run(...).stdoutsites, bothgit ls-filesinsidetry/exceptwithcheck=Trueand anrglobfallback — a git failure raises and is handled, not swallowed.Refs #2189, #2187
Closes #2193
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