GitHub - david-shmailov/CPU_task3_MIPS: We implemented a single cycle version of the MIPS CPU in VHDL code, under the simplification of 1 cycle memory delay, a reduced instruction set defined by the assignment, and 10-bit memory space. We then used the Quartus FPGA chipset to verify the design. By David Shmailov and Aviram Lachmani

Name		Name	Last commit message	Last commit date
CODE		CODE
DOC		DOC
Quartus		Quartus
SIM		SIM
TB		TB
VHDL		VHDL

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We implemented a single cycle version of the MIPS CPU in VHDL code, under the simplification of 1 cycle memory delay, a reduced instruction set defined by the assignment, and 10-bit memory space. We then used the Quartus FPGA chipset to verify the design. By David Shmailov and Aviram Lachmani

design digital-architecture fpga mips mips-architecture quartus verification vhdl

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