Jihun Chae Β· μ±μ§ν
Undergraduate in Electrical and Electronics Engineering at Chung-Ang University, graduating February 2027. I design digital hardware for AI and signal workloads β convolution engines, fixed-point datapaths, and the testbenches that prove they match a software reference bit for bit.
Most of my work sits between the RTL and the system around it: quantisation constants, bus interfaces, timing closure, golden-model verification. I have taken a design from Verilog to a placed-and-routed layout, and from a bitstream to a working board demonstration.
| Degree | Institution | Period |
|---|---|---|
| B.S. in Electrical and Electronics Engineering | Chung-Ang University, College of ICT Engineering | 2021.03 β 2027.02 (expected) |
Military service 2023.03 β 2024.09.
| Role | Institution | Topic | Period |
|---|---|---|---|
| Summer Research Intern | Seoul National University, Dept. of Electrical and Computer Engineering | FPGA self-attention accelerator (integer-only QKα΅, softmax, ΓV) | 2026.06 β 2026.07 |
| Undergraduate Researcher | Seoul National University, Dept. of Electrical and Computer Engineering | FPGA technical-indicator accelerator with deterministic latency | 2026.03 β 2026.06 |
| Project | What it is | Stack |
|---|---|---|
| YOLOv2 FPGA Accelerator | A 22-layer object detector fitted onto a single Artix-7, verified layer by layer | Verilog, Vivado, MicroBlaze |
| HFT Indicator Accelerator | Bollinger, MACD and RSI fused into one trading decision at fixed latency | Verilog, C, Vivado |
| FPGA Self-Attention Accelerator | QKα΅, softmax and the value multiply verified against a Python golden model | Verilog, Python |
| Project | What it is | Stack |
|---|---|---|
| 16Γ16 Matrix Multiply ASIC | Fixed-point matrix multiplier behind an SRAM interface, two MACs per cycle, no bubbles | Verilog, Vivado |
| CNN Convolution Accelerator | Three-channel 5Γ5 stride-3 convolution taken from RTL to place-and-route | Verilog, OpenROAD, Nangate45 |
| Project | What it is | Stack |
|---|---|---|
| K-means FPU Accelerator | IEEE-754 FPU on APB replacing the software float path of a RISC-V core | Verilog, C, APB |
| APB Custom IP | Two memory-mapped accelerators β byte-parallel addition and a 128-bit SIMD MAC | Verilog, C |
| Project | What it is | Stack |
|---|---|---|
| Strawberry Sorting System | Three heterogeneous boards tied into one line over CAN and IPC | C, Python, CAN, FreeRTOS |
| Smart Sunshade | A public sunshade that tracks the sun and folds itself in wind | Arduino, ESP8266 |
| Project | What it is | Stack |
|---|---|---|
| MNIST / ResNet50 Transfer | Hyperparameter analysis and a controlled comparison against a 23.5M-parameter backbone | PyTorch |
| Project | Result |
|---|---|
| YOLOv2 | all 22 layers on one Artix-7, 0 mismatch against the C reference layer by layer; WNS β0.18 ns at 81.25 MHz |
| HFT | 890 ns latency regardless of a 7,700Γ price range; 33 β 100 MHz, zero timing violations |
| Attention | a full attention head at 118.2 MHz using ~10% of the device, 1,024 outputs verified on board |
| Matmul ASIC | 2,048 of 2,051 cycles active (99.85%), all 256 golden values matched |
| Convolution | scored area 295,842 β 106,234 Β΅mΒ² (2.8Γ), score 41.3 β 33.1; physical implementation signed off with +0.10 ns worst-path slack and zero DRC at 1 GHz |
| K-means FPU | 187.75 ms β 60.02 ms (3.13Γ) measured on the board |
| Strawberry sorting | three boards and three protocols behind one command; exactly one actuation per strawberry at 2 fps |
| Transfer learning | 100% from 4,098 trained parameters (0.017%); training all 23.5M gave 66.67% |
| Award | Competition | Date |
|---|---|---|
| Encouragement Award (of 19 teams) | 2026 Deep Learning Hardware Design Competition | 2026.06 |
- The effect of university students' degree of AI use on AI literacy and productivity, Journal of Artificial Intelligence Humanities, Vol. 21 (KCI-listed), 2025.12 β co-author. Responsible for the introduction, theoretical background, interview instrument design and the interviews themselves.
| Languages | Verilog Β· C, C++ Β· Python (PyTorch, NumPy) Β· shell |
| Environment | Linux (Ubuntu, Yocto, WSL), Git, Makefile |
| EDA | Vivado, Questa / ModelSim, NCverilog, OpenROAD, Icarus |
| Hardware | AXI4 / AXI4-Lite / APB, CAN, UART, I2C, DMA, FSM design, pipelining, timing closure |
| Platforms | Artix-7 (Nexys A7), MicroBlaze, RISC-V SoC, FreeRTOS, Arduino / ESP8266 |
Top languages β by source bytes across the repositories above
Verilog ββββββββββββββββββββββββββββββ 57%
C ββββββββββββββββββββββββββββββ 26%
Python ββββββββββββββββββββββββββββββ 7%
Tcl ββββββββββββββββββββββββββββββ 5%
C++ ββββββββββββββββββββββββββββββ 2%
Most used topics β verilog Β· fpga Β· rtl Β· asic Β· risc-v Β· fixed-point Β· embedded Β· pytorch
| Certificate | Score / Grade | Date |
|---|---|---|
| TOEIC | 910 (LC 475 / RC 435) | 2024.12 |
| Driver's licence, Class 2 Regular | β | 2021.07 |
Each repository ships English and Korean READMEs. Files marked as distributed material in a repository were provided by a course or competition and are included only so the project builds; check their original licence before reuse. Everything else is my own work, and team projects state my scope in their README.