Pinned Loading

1. uC-chip-interface-arduino uC-chip-interface-arduino Public

   A PC interface for async and neuromrphic IC testing

   Python 2 3

2. actlib-neurosynaptic-periphery actlib-neurosynaptic-periphery Public

   Verilog 1 1

3. lib-test-components lib-test-components Public

   This is a test bench library for use with async DUTs for both actsim CHP, actsim PRS and Cadence AMS simulations (or other verilog simulators). The test benches are supposed to be modular and are c…

   Verilog