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Display Histogram is an array of bins and can be generated in many ways
referred to as modes.
Ex: HSV max(RGB), Wighted RGB etc.
Understanding the histogram data format(Ex: HSV max(RGB))
Histogram is just the pixel count.
For a maximum resolution of 10k (10240 x 4320 = 44236800)
25 bits should be sufficient to represent this along with a buffer of 7
bits(future use) u32 is being considered.
max(RGB) can be 255 i.e 0xFF 8 bit, considering the most significant 5
bits, hence 32 bins.
Below mentioned algorithm illustrates the histogram generation in
hardware.
hist[32] = {0};
for (i = 0; i < resolution; i++) {
bin = max(RGB[i]);
bin = bin >> 3; /* consider the most significant bits */
hist[bin]++;
}
If the entire image is Red color then max(255,0,0) is 255 so the pixel
count of each pixels will be placed in the last bin. Hence except
hist[31] all other bins will have a value zero.
Generated histogram in this case would be hist[32] = {0,0,....44236800}
Description of the structures, properties defined are documented in the
header file include/uapi/drm/drm_mode.h
v8: Added doc for HDR planes, removed reserved variables (Dmitry)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
ImageEnhancemenT(IET) hardware interpolates the LUT value to generate the enhanced output image. LUT takes an input value, outputs a new value based on the data within the LUT. 1D LUT can remap individual input values to new output values based on the LUT sample. LUT can be interpolated by the hardware by multiple modes Ex: Direct Lookup LUT, Multiplicative LUT etc The list of supported mode by hardware along with the format(exponent mantissa) is exposed to user by the iet_lut_caps property. Maximum format being 8.24 i.e 8 exponent and 24 mantissa. For illustration a hardware supporting 1.9 format denotes this as 0x10001FF. In order to know the exponent do a bitwise AND with 0xF000000. The LUT value to be provided by user would be a 10bit value with 1 bit integer and 9 bit fractional value. Multiple formats can be supported, hence pointer is used over here. User can then provide the LUT with any one of the supported modes in any of the supported formats. The entries in the LUT can vary depending on the hardware capability with max being 255. This will also be exposed as iet_lut_caps so user can generate a LUT with the specified entries. v8: define enum for iet_mode, add more doc for iet modes (Dmitry) Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Add drm-crtc property for histogram and for the properties added add the corresponding get/set_property. v8: Rebased Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Add drm-crtc property for IET 1DLUT and for the properties added add corresponding get/set_property. Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Add the register/bit definitions for global histogram. v2: Intended the register contents, removed unused regs (Jani) Bspec: 4270 Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Statistics is generated from the image frame that is coming to display
and an event is sent to user after reading this histogram data.
v2: forward declaration in header file along with error handling (Jani)
v3: Replaced i915 with intel_display (Suraj)
v4: Removed dithering enable/disable (Vandita)
New patch for histogram register definitions (Suraj)
v5: IET LUT pgm follow the seq in spec and removed change to TC at end
(Suraj)
v8: Retained only the Histogram part and move IET LUT to a different
patch.
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Histogram added as part of i915/display driver. Adding the same for xe as well. Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Upon enabling histogram an interrupt is trigerred after the generation
of the statistics. This patch registers the histogram interrupt and
handles the interrupt.
v2: Added intel_crtc backpointer to intel_histogram struct (Jani)
Removed histogram_wq and instead use dev_priv->unodered_eq (Jani)
v3: Replaced drm_i915_private with intel_display (Suraj)
Refactored the histogram read code (Jani)
v4: Rebased after addressing comments on patch 1
v5: removed the retry logic and moved to patch7 (Jani)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Handle histogram caps and histogram config property in i915 driver. Fill the histogram hardware capability and act upon the histogram config property to enable/disable histogram in i915. Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
User created LUT can be fed back to the hardware so that the hardware can apply this LUT data to see the enhancement in the image. Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Upon drm getting the IET LUT value from the user through the IET_LUT property, i915 driver will write the LUT table to the hardware registers. Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
The delay counter for histogram does not reset and as a result the histogram bin never gets updated. Workaround would be to use save and restore histogram register. v2: Follow the seq in interrupt handler Restore DPST bit 0 read/write dpst ctl rg Restore DPST bit 1 and Guardband Delay Interrupt counter = 0 (Suraj) v3: updated wa version for display 13 and 14 Wa: 14014889975 Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
In Display 20+, new registers are added for setting index, reading histogram and writing the IET. v2: Removed duplicate code (Jani) v3: Moved histogram core changes to earlier patches (Jani/Suraj) v4: Rebased after addressing comments on patch 1 v5: Added the retry logic from patch3 and rebased the patch series v6: optimize wite_iet() (Suraj) Bspec: 68895 Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Enable pipe dithering while enabling histogram to overcome some atrifacts seen on the screen. Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
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Pull request overview
This PR introduces a new DRM/KMS histogram (and related image-enhancement LUT) UAPI and wires it up as optional CRTC properties, with an initial i915 implementation that programs DPST/GLOBAL_HIST hardware and delivers histogram readiness via uevent + blob property updates.
Changes:
- Add new UAPI structs/enums for histogram + IET LUT capability/config/data blobs.
- Add new optional CRTC properties (caps/enable/data + IET LUT caps/data) and atomic plumbing for setting/getting blobs.
- Implement i915-side histogram IRQ handling, workqueue readout, property updates, and Makefile wiring.
Reviewed changes
Copilot reviewed 15 out of 15 changed files in this pull request and generated 23 comments.
Show a summary per file
| File | Description |
|---|---|
| include/uapi/drm/drm_mode.h | Adds new histogram + IET LUT UAPI structs/enums. |
| include/drm/drm_crtc.h | Extends CRTC state/object with histogram/IET properties and create helpers. |
| drivers/gpu/drm/xe/Makefile | Builds the new intel_histogram.o for XE display. |
| drivers/gpu/drm/i915/Makefile | Builds the new intel_histogram.o for i915. |
| drivers/gpu/drm/i915/display/intel_histogram.h | Declares i915 histogram interface/constants. |
| drivers/gpu/drm/i915/display/intel_histogram.c | Implements histogram enable/disable, IRQ/work readout, IET LUT programming. |
| drivers/gpu/drm/i915/display/intel_histogram_regs.h | Adds DPST/GLOBAL_HIST register definitions. |
| drivers/gpu/drm/i915/display/intel_display.c | Hooks histogram atomic check + commit-tail update calls. |
| drivers/gpu/drm/i915/display/intel_display_types.h | Adds struct intel_histogram * to struct intel_crtc. |
| drivers/gpu/drm/i915/display/intel_display_regs.h | Adds histogram event bits for pipe IRQ handling. |
| drivers/gpu/drm/i915/display/intel_display_irq.c | Dispatches histogram pipe IRQ to i915 handler; enables the IRQ bit. |
| drivers/gpu/drm/i915/display/intel_crtc.c | Initializes histogram + creates new CRTC properties during CRTC init; frees on teardown. |
| drivers/gpu/drm/drm_crtc.c | Adds core helpers to create the new CRTC properties. |
| drivers/gpu/drm/drm_atomic_uapi.c | Adds atomic set/get handling for the new CRTC blob properties. |
| drivers/gpu/drm/drm_atomic_state_helper.c | Updates CRTC state duplication/destruction for the new blob fields/flags. |
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| __u64 hist_mode_data; | ||
| __u32 nr_hist_mode_data; | ||
| enum drm_mode_histogram hist_mode; | ||
| bool enable; | ||
| }; |
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| struct drm_iet_1dlut_sample { | ||
| __u64 iet_lut; | ||
| __u32 nr_elements; | ||
| enum drm_iet_mode iet_mode; | ||
| }; |
| */ | ||
| struct drm_property *histogram_enable_property; | ||
| /** | ||
| * @histogram_data_proeprty: Optional CRTC property for getting the |
| */ | ||
| struct drm_property *iet_lut_caps_property; | ||
| /** | ||
| * @iet_lut_proeprty: Optional CRTC property for writing the |
Comment on lines
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| char *event[3] = {NULL, NULL, NULL}; | ||
| int retry; | ||
|
|
||
| event[0] = "HISTOGRAM=1"; | ||
| event[1] = kasprintf(GFP_KERNEL, "PIPE=%d", intel_crtc->pipe); | ||
| event[2] = NULL; | ||
|
|
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| blob = drm_property_create_blob(crtc->dev, | ||
| sizeof(struct drm_iet_caps), | ||
| NULL); | ||
| if (IS_ERR(blob)) | ||
| return -1; |
Comment on lines
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| histogram = kzalloc(sizeof(*histogram), GFP_KERNEL); | ||
| if (!histogram) | ||
| return -ENOMEM; | ||
| histogram_caps = kzalloc(sizeof(*histogram_caps), GFP_KERNEL); | ||
| if (!histogram_caps) | ||
| return -ENOMEM; | ||
|
|
||
| histogram_caps->histogram_mode = DRM_MODE_HISTOGRAM_HSV_MAX_RGB; | ||
| histogram_caps->bins_count = HISTOGRAM_BIN_COUNT; | ||
|
|
||
| iet_caps = kzalloc(sizeof(*iet_caps), GFP_KERNEL); | ||
| if (!iet_caps) | ||
| return -ENOMEM; |
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| * @iet_lut_caps: | ||
| * | ||
| * The blob points to the structure drm_iet_lut_caps. | ||
| * For more info on the elements of the struct drm_iet_lut_caps | ||
| * see include/uapi/drm/drm_mode.h | ||
| */ | ||
| struct drm_property_blob *iet_lut_caps; |
Comment on lines
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| /** | ||
| * @iet_lut: | ||
| * | ||
| * The blob points to the struct drm_lut_sample | ||
| * For more information on the elements of struct drm_lut_sample | ||
| * see include/uapi/drm/drm_mode.h | ||
| */ | ||
| struct drm_property_blob *iet_lut; |
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| drm_property_replace_global_blob(display->drm, | ||
| &intel_crtc->base.state->histogram_data, | ||
| sizeof(struct drm_histogram), | ||
| hist, &intel_crtc->base.base, | ||
| intel_crtc->base.histogram_data_property); |
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Before writing the IET LUT data exit PSR to allow updation of the enhanced image. Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
After writing the IET LUT data provided by the user, if backlight needs to be updated for eDP update the backlight. Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Upon enabling the histogram selective fetch, for generation of histogram only the provided co-ordinates will be considered and not the entire pipe source region. Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
On enabling histogram use the lowest possible guardband threshold and guradband delay to allow histogram generation as soon as possible. Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
With PSR/PR active use 1% guardband threshold and 0x01 guardband delay to accomodate histogram generation with samll statistical change. On LNL+ platform guardband lower threshold is used and platforms prior to LNL a low threshold is used. Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
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