Three phase (3-PH) DSOGI Phase Lock Loop (PLL)

Dependencies

Angle Lock
Phase Swap Detection
Realtime Phase Fault Detection
Generated Code
Code Tested on STM32F7 (code on stm32.zip)
Not using Volder's algorithm instead using approximations requiering a sampling of 10kHz

Worse case, when the phase of the Voltage phase is pi radians of offset at the start, thus having the maximum error.

65Hz input

55Hz input

45Hz input

Name		Name	Last commit message	Last commit date
code_gen		code_gen
derived		derived
dsogi_pll_3ph_top_ert_rtw		dsogi_pll_3ph_top_ert_rtw
resources/project		resources/project
slprj		slprj
LICENSE		LICENSE
Pll_3phase_dsogi.prj		Pll_3phase_dsogi.prj
README.md		README.md
dictionary.sldd		dictionary.sldd
dsogi.slx		dsogi.slx
dsogi_pll.mlx		dsogi_pll.mlx
dsogi_pll_3ph.slx		dsogi_pll_3ph.slx
dsogi_pll_3ph.slxc		dsogi_pll_3ph.slxc
dsogi_pll_3ph_Harness1_HarnessInputs.mat		dsogi_pll_3ph_Harness1_HarnessInputs.mat
dsogi_pll_3ph_Harness2_HarnessInputs.mat		dsogi_pll_3ph_Harness2_HarnessInputs.mat
dsogi_pll_3ph_Harness2_HarnessInputs_1.mat		dsogi_pll_3ph_Harness2_HarnessInputs_1.mat
dsogi_pll_3ph_Harness3_HarnessInputs.mat		dsogi_pll_3ph_Harness3_HarnessInputs.mat
dsogi_pll_3ph_Harness4_HarnessInputs.mat		dsogi_pll_3ph_Harness4_HarnessInputs.mat
dsogi_pll_3ph_sbs.mexw64		dsogi_pll_3ph_sbs.mexw64
dsogi_pll_3ph_sfun.mexw64		dsogi_pll_3ph_sfun.mexw64
dsogi_pll_3ph_top.slx		dsogi_pll_3ph_top.slx
dsogi_pll_3ph_top.slxc		dsogi_pll_3ph_top.slxc
dsogi_pll_3ph~mdl.slmx		dsogi_pll_3ph~mdl.slmx
dsogi_pll_arch.slx		dsogi_pll_arch.slx
dsogi_pll_arch~mdl.slmx		dsogi_pll_arch~mdl.slmx
gen_code.m		gen_code.m
requierements.slreqx		requierements.slreqx
smt32.zip		smt32.zip
test_3phases_voltages.m		test_3phases_voltages.m
test_files.mldatx		test_files.mldatx
test_files~mldatx.slmx		test_files~mldatx.slmx
xcopy.bat		xcopy.bat