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Guo Sufeng aHappend

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Undergraduate - Nanjing University · Integrated Circuit Design & Integrated Systems · Building autonomous AI systems and AI accelerators @Argus-AiTeam

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Nanjing University
Jiangsu, CHINA
07:25 (UTC +08:00)
https://linktr.ee/sufeng_guo
@hapouterwall
hapouterwall
@hapouterwall
https://ahappend.github.io/

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Achievements

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aHappend/README.md

Hi, I'm Sufeng Guo

Undergraduate at Nanjing University (Integrated Circuit Design and Integrated Systems), graduating in 2027.

I work on autonomous AI systems, AI accelerators, computer architecture, and hardware-software co-design.

Personal website: ahappend.github.io

Education

Nanjing University — Integrated Circuit Design and Integrated Systems
Expected graduation: 2027

Interests

Autonomous AI DNN Mapping Scheduling NoC RTL Edge AI Reproducible Systems

Currently Working On

DNN mapping and inter-layer scheduling for tiled accelerators
Hardware-software co-design for AI accelerators
Evidence-driven autonomous research and engineering systems

Projects

Argus/original/Argus Agent/Microsoft - Open multi-agent runtime for long-horizon research and engineering, combining persistent state, reviewed execution, verification, and evidence. Here is the Technical Report.
ACE-2/personal/ACE-2/organization - Argus-built Qwen2.5-0.5B W4A8 accelerator with SystemVerilog RTL, certified two-token integration, SKY130 100 MHz results, and evidence-first host-trust recovery.
64-Point FFT - Resource-efficient radix-2 DIT FFT in SystemVerilog using folded streaming SDF RTL, Q1.15 fixed-point arithmetic, Vivado/XSim simulation, Python/NumPy co-verification, and Virtex-7 implementation results.
Two-Stage CMOS Op-Amp - Two-stage CMOS operational amplifier in TSMC 0.18 um technology, with Miller compensation, Spectre AC/DC/transient verification, and analysis of gain, bandwidth, phase margin, slew rate, output swing, and power.

Publications

HyperCut: Fast Inter-Layer Scheduling via Directed Hypergraph and Early Filtering — Academic paper on early filtering and hypergraph-based inter-layer scheduling for tiled DNN accelerators.
arXiv: https://arxiv.org/abs/2608.19296
Argus: A General-Purpose Agentic Reasoning Runtime for Long-Horizon Tasks — Technical report on a persistent, self-evolving runtime for long-horizon agentic reasoning.
arXiv: https://arxiv.org/abs/2608.05144

Research Profiles

Tools

Python C/C++ TypeScript Verilog React Linux

Contact

Feel free to contact me!

Email/school(Nanjing University) sufeng_guo@smail.nju.edu.cn
Email/gmail hapouterwall@gmail.com
Email/qq sufeng_guo@qq.com

Popular repositories Loading

Hardware-Implementation-and-Optimization-of-64-Point-FFT Hardware-Implementation-and-Optimization-of-64-Point-FFT Public

Resource-efficient 64-point radix-2 DIT FFT in SystemVerilog: folded streaming SDF RTL, Q1.15 fixed-point arithmetic, Vivado/XSim simulation, Python/NumPy co-verification, and Virtex-7 implementati…

C
SET-NN-Mapping-Scheduling SET-NN-Mapping-Scheduling Public

Exploring the impact of neural network task granularity on mapping and scheduling efficiency on multi-core NoC architectures based on the SET framework.
Crane Crane Public

This repository contains a reproducible Python implementation of the Crane scheduling workflow for DNN pipeline scheduling experiments.

Python
design-and-simulation-of-a-two-stage-cmos-operational-amplifier design-and-simulation-of-a-two-stage-cmos-operational-amplifier Public

Two-stage CMOS operational amplifier designed in TSMC 0.18 um technology, with Spectre AC/DC/transient verification, Miller compensation, and analysis of gain, bandwidth, phase margin, slew rate, o…

TeX
ace-2 ace-2 Public

Argus-built, evidence-first Qwen2.5-0.5B W4A8 accelerator: certified two-token RTL integration, SKY130 100 MHz, and Fresh-L2-accepted V8 host-trust recovery.

SystemVerilog 1
aHappend aHappend Public

Sufeng Guo - personal profile