Early-career software and computer-architecture engineer from Córdoba, Argentina, drawn to the layer where software meets silicon. Completing a Computer Science degree (Licenciatura en Ciencias de la Computación) at FaMAF, Universidad Nacional de Córdoba.
I like low-level performance work: reading pipeline traces, figuring out where cycles disappear, and making a simulator's numbers agree with real hardware.
Through the FaMAF CVA6 Project, two browser-based pipeline visualisers for RISC-V cores:
- MinorFlow: reconstructs the gem5 MinorCPU pipeline, cycle by cycle, from gem5 debug traces.
- CVA6Flow: the RTL sibling, for the CORE-V CVA6 core simulated in Verilator, straight off the VCD signals.
They exist to answer one question: how closely can a gem5 configuration be made to match a real RISC-V core?
C++, C, Python, Haskell, gem5, Verilator, SystemVerilog, Docker, Git, Linux, and the RISC-V toolchain.
