I am an Electronics and Communication Engineering student passionate about RTL Design, FPGA Development, ASIC Implementation, and Digital System Design. My work focuses on translating digital concepts into synthesizable hardware using Verilog HDL and industry-standard EDA tools.
My technical focus spans the full digital design stack — from RTL specification and functional simulation through synthesis, placement, routing, and GDSII generation. I actively prototype digital systems on Xilinx FPGA platforms, validate designs through hardware-in-loop debugging using Vivado VIO, and explore open-source ASIC flows including OpenLane and OpenROAD.
Focus Areas:
- RTL Design — synthesizable Verilog for real hardware targets
- FPGA Prototyping — Xilinx Vivado, constraint-driven implementation, VIO-based hardware validation
- Digital Design — combinational and sequential logic, FSM architecture, timing closure
- Functional Verification — self-checking testbenches, waveform analysis, corner-case coverage
- ASIC Design Flow — synthesis, floorplan, placement, routing, GDSII via OpenLane / Cadence
- RISC-V Architecture — ISA study, processor microarchitecture, SoC design fundamentals
- Open-Source EDA — Yosys, OpenROAD, Magic, OpenLane
| Domain | Proficiency | Details |
|---|---|---|
| RTL Design | Advanced | Synthesizable Verilog RTL targeting Xilinx and open-source ASIC flows |
| FPGA Design | Advanced | Xilinx Boolean board, Vivado constraint-driven implementation, VIO hardware validation |
| Digital Logic Design | Advanced | Combinational and sequential circuits, timing analysis, critical path optimization |
| FSM Design | Advanced | Moore and Mealy FSMs, multi-state control logic, glitch-free output encoding |
| UART Protocol | Advanced | Full TX/RX implementation, baud generation, multi-module integration on FPGA |
| I²C Protocol | Intermediate | I²C Master controller, 16-state FSM, multi-byte read/write, ACK/NACK handling |
| ASIC Design Flow | Intermediate | RTL → Synthesis → Floorplan → P&R → GDSII via OpenLane / Cadence Genus + Innovus |
| Verification | Intermediate | Self-checking testbenches, waveform analysis, VIO-based hardware-in-loop testing |
| RISC-V Architecture | Exploring | ISA study, microarchitecture fundamentals, SoC integration concepts |
Bluetooth-Enabled UART Memory Transmitter on FPGA
A complete FPGA system integrating a UART transmitter, memory controller, and Bluetooth communication link using the HC-05 module. Designed and validated entirely on a Xilinx Boolean FPGA board using Vivado VIO for hardware-in-loop debugging of FSM state transitions and handshake signals.
| Category | Details |
|---|---|
| Technology Stack | Verilog HDL, Xilinx Vivado, Xilinx Boolean FPGA, HC-05 Bluetooth Module |
| Design Methodology | Modular RTL architecture — UART TX, baud generator, memory controller, top-level integration |
| Verification | Vivado functional simulation, VIO-based hardware debugging, waveform analysis |
| Hardware / Simulation | Validated on physical FPGA hardware; multi-module FSM and handshake signals verified via VIO |
| Repository | Bluetooth-Enabled-UART-Transmitter-on-FPGA |
Parity Checker FSM
A Moore FSM-based serial parity checker implementing even and odd parity detection over a serial input stream. Designed for correctness in both simulation and synthesis, with structured functional verification confirming state transitions and output accuracy.
| Category | Details |
|---|---|
| Technology Stack | Verilog HDL, Icarus Verilog / ModelSim, GTKWave |
| Design Methodology | Moore FSM architecture with clean state encoding and single-cycle output response |
| Verification | Directed testbench covering even/odd parity sequences and edge cases; waveform validation |
| Hardware / Simulation | Simulation-verified; synthesizable RTL suitable for FPGA implementation |
| Repository | Parity-Checker-FSM |
N-bit Up/Down Counter — Full ASIC Implementation
A parameterized N-bit up/down counter taken through the complete RTL-to-GDSII flow using the OpenLane open-source ASIC toolchain. Covers synthesis, floorplanning, placement, routing, and final GDSII generation — demonstrating end-to-end ASIC design methodology.
| Category | Details |
|---|---|
| Technology Stack | Verilog HDL, OpenLane, Yosys, OpenROAD, Magic VLSI |
| Design Methodology | Parameterized RTL design enabling configurable bit-width; full physical implementation flow |
| Verification | Pre-synthesis simulation; post-synthesis netlist verification |
| Hardware / Simulation | GDSII generated via OpenLane; layout reviewed in Magic VLSI |
| Repository | N-bit-up-down-counter |
I²C Master Controller — Verilog RTL Design
A complete I²C Master controller implemented in Verilog RTL, featuring a 16-state FSM that manages the full I²C transaction lifecycle including START, address phase, data phase, ACK/NACK handling, and STOP generation. Supports both read and write operations with configurable slave addressing.
| Category | Details |
|---|---|
| Technology Stack | Verilog HDL, Icarus Verilog / ModelSim, GTKWave |
| Design Methodology | 16-state Moore FSM; explicit SCL/SDA drive logic; ACK/NACK detection and retry handling |
| Verification | Directed simulation covering single-byte and multi-byte read/write; ACK/NACK edge cases |
| Hardware / Simulation | Simulation-verified RTL; designed for FPGA deployment with compatible I²C peripherals |
| Repository | i2c-master-verilog |
An ongoing study of the RISC-V open ISA as a foundation for understanding processor design and SoC architecture.
| Area | Status | Notes |
|---|---|---|
| ISA Study | In Progress | RV32I base integer instruction set; instruction encoding and decoding |
| Processor Fundamentals | In Progress | Datapath organization, pipeline stages, hazard classification |
| Microarchitecture Concepts | Exploring | Single-cycle and multi-cycle datapath design |
| SoC Design Concepts | Exploring | Bus interconnects, memory-mapped I/O, peripheral integration |
The goal is to build toward a functioning RISC-V core in Verilog — unifying RTL design skills with processor architecture understanding.
Mohanapriyan P RTL Design Engineer Candidate | FPGA Developer | Digital Design Enthusiast
Focus Areas:
- RTL Design and Synthesis
- FPGA Development and Hardware Validation
- Digital Verification (Simulation and Hardware-in-Loop)
- ASIC Physical Design Flow
- Open-Source EDA and Semiconductor Research
Industry Recognition:
- TOPS (Tamil Nadu Opportunities for Students) — First Round Cleared
Completed
| Platform | Certification |
|---|---|
| NPTEL | Forests and Their Environment |
Planned
| Certification | Platform |
|---|---|
| VLSI Design Fundamentals | NPTEL / Coursera |
| Digital IC Design | NPTEL |
| SystemVerilog for Verification | Udemy / Online |
| Functional Verification Methodology | Industry / NPTEL |
learning:
- Verilog HDL — advanced RTL patterns and synthesis-aware coding
- SystemVerilog — moving toward structured verification
- Digital Design — timing analysis, clock domain crossing, metastability
building:
- FPGA projects targeting Xilinx Boolean board
- Communication protocol IP cores (UART, I2C, SPI)
exploring:
- Functional verification methodology
- ASIC design flow — Cadence and open-source (OpenLane / OpenROAD)
- RISC-V processor architecture and implementation
open_to:
- VLSI / RTL Design Internships
- FPGA Development Opportunities
- Semiconductor Research Collaborations
- Open-Source EDA and Chip Design Contributions
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"Designing reliable hardware today for the intelligent systems of tomorrow."