CPU

~~This is a simple CISC architecture~~

This is being completely redone and is now a RISC-V implementation

Name		Name	Last commit message	Last commit date
Latest commit History 12 Commits
ModelSim		ModelSim
_src		_src
src		src
vga_adapter		vga_adapter
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md
alu.v		alu.v
control_signals.vh		control_signals.vh
controller.v		controller.v
cpu.v		cpu.v
datapath.v		datapath.v
extend.v		extend.v
ff.v		ff.v
mem_ctrl.v		mem_ctrl.v
mux.v		mux.v
parameters.vh		parameters.vh
ram512x32.mif		ram512x32.mif
ram512x32.v		ram512x32.v
register_file.v		register_file.v
top.v		top.v
vga_writer.v		vga_writer.v

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