GitHub - IT-Forrest/CPU_design: Verilog of a tapeout reprogrammable chip for analog circuit auto-tuning

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 152 Commits
bscript		bscript
macros		macros
mscript		mscript
readme		readme
script1115		script1115
script815		script815
script_130		script_130
sim		sim
.gitignore		.gitignore
AT_compile_all.do		AT_compile_all.do
AT_file_handle.do		AT_file_handle.do
AT_testcase_flow.do		AT_testcase_flow.do
AT_try.do		AT_try.do
CPU_wjf.cr.mti		CPU_wjf.cr.mti
CPU_wjf.mpf		CPU_wjf.mpf
CTRL_LOGIC.v		CTRL_LOGIC.v
DEFINE_CPU.v		DEFINE_CPU.v
D_MEMORY.v		D_MEMORY.v
Doxyfile		Doxyfile
I_MEMORY.v		I_MEMORY.v
I_MEMORY_8bit.v		I_MEMORY_8bit.v
I_MEMORY_CF_OSCD_TASK_8BIT.v		I_MEMORY_CF_OSCD_TASK_8BIT.v
I_MEMORY_CF_TASK_8BIT.v		I_MEMORY_CF_TASK_8BIT.v
I_MEMORY_MULTI_SA_SS_TASK_8BIT.v		I_MEMORY_MULTI_SA_SS_TASK_8BIT.v
I_MEMORY_MULTI_SA_TASK_8BIT.v		I_MEMORY_MULTI_SA_TASK_8BIT.v
I_MEMORY_SA_TASK_8BIT.v		I_MEMORY_SA_TASK_8BIT.v
PIPE_CPU.v		PIPE_CPU.v
PIPE_CPU_TOP.v		PIPE_CPU_TOP.v
PSEUDO_SPI_INTF.v		PSEUDO_SPI_INTF.v
RA1SHD_IBM1024X8.v		RA1SHD_IBM1024X8.v
RA1SHD_ibm512x8.v		RA1SHD_ibm512x8.v
SCPU_8BIT_ALU_CTRL_SPI.v		SCPU_8BIT_ALU_CTRL_SPI.v
SCPU_SRAM_8BIT_ALU_SPI_TOP.v		SCPU_SRAM_8BIT_ALU_SPI_TOP.v
SCPU_SRAM_8BIT_ALU_SPI_TOP.vg		SCPU_SRAM_8BIT_ALU_SPI_TOP.vg
SCPU_SRAM_8BIT_ALU_SPI_TOP_VG.v		SCPU_SRAM_8BIT_ALU_SPI_TOP_VG.v
SCPU_SRAM_8BIT_ALU_SPI_TOP_VGA.v		SCPU_SRAM_8BIT_ALU_SPI_TOP_VGA.v
SC_CELL_V3.v		SC_CELL_V3.v
SERIAL_CPU.v		SERIAL_CPU.v
SERIAL_CPU_8bit.v		SERIAL_CPU_8bit.v
SHARE_SUPERALU.v		SHARE_SUPERALU.v
SRAM_IO_CTRL.v		SRAM_IO_CTRL.v
SRAM_IO_CTRL_LOGIC.v		SRAM_IO_CTRL_LOGIC.v
SRAM_IO_CTRL_SHELL.v		SRAM_IO_CTRL_SHELL.v
alu_cpu_mem.do		alu_cpu_mem.do
ibm13rfrvt.v		ibm13rfrvt.v
ibm13rfrvt_neg.v		ibm13rfrvt_neg.v
iogpil_cmrf8sf_rvt.v		iogpil_cmrf8sf_rvt.v
pcpu_alu_test.do		pcpu_alu_test.do
pcpu_ctrl_test.do		pcpu_ctrl_test.do
pcpu_loop_test.do		pcpu_loop_test.do
pcpu_sa_test.do		pcpu_sa_test.do
pcpu_single_mem_test.do		pcpu_single_mem_test.do
pcpu_single_test.do		pcpu_single_test.do
pseudo_spi_intf_ra1512_test.do		pseudo_spi_intf_ra1512_test.do
pseudo_spi_intf_scan_test.do		pseudo_spi_intf_scan_test.do
pseudo_spi_intf_test.do		pseudo_spi_intf_test.do
scpu_io_ctrl_ra1512_serial8bit_alu_spi_top_mux_test.do		scpu_io_ctrl_ra1512_serial8bit_alu_spi_top_mux_test.do
scpu_io_ctrl_ra1512_serial8bit_alu_spi_top_mux_vg_test.do		scpu_io_ctrl_ra1512_serial8bit_alu_spi_top_mux_vg_test.do
scpu_io_ctrl_ra1512_serial8bit_alu_spi_top_test.do		scpu_io_ctrl_ra1512_serial8bit_alu_spi_top_test.do
scpu_io_ctrl_ra1512_serial8bit_alu_top_test.do		scpu_io_ctrl_ra1512_serial8bit_alu_top_test.do
scpu_loop_test_serial.do		scpu_loop_test_serial.do
scpu_loop_test_serial8bit.do		scpu_loop_test_serial8bit.do
scpu_mem_inst_end_test_serial8bit.do		scpu_mem_inst_end_test_serial8bit.do
scpu_mimic_cf_top_oscd_sweep_test.do		scpu_mimic_cf_top_oscd_sweep_test.do
scpu_mimic_cf_top_test.do		scpu_mimic_cf_top_test.do
scpu_mimic_multi_sa_top_test.do		scpu_mimic_multi_sa_top_test.do
scpu_mimic_sa_top_test.do		scpu_mimic_sa_top_test.do
scpu_single_test_serial8bit.do		scpu_single_test_serial8bit.do
sram_io_ctrl_logic_test.do		sram_io_ctrl_logic_test.do
sram_io_ctrl_ra1512_serial8bit_test.do		sram_io_ctrl_ra1512_serial8bit_test.do
sram_io_ctrl_ra1512_test.do		sram_io_ctrl_ra1512_test.do
sram_io_ctrl_test.do		sram_io_ctrl_test.do
sys_pc_ctrl_clock_once_test.do		sys_pc_ctrl_clock_once_test.do
sys_pc_mem_loop_8bit_test.do		sys_pc_mem_loop_8bit_test.do
sys_pc_pause_cpu_resume_test.do		sys_pc_pause_cpu_resume_test.do
sys_pc_pause_cpu_resume_vg_test.do		sys_pc_pause_cpu_resume_vg_test.do
sys_pc_pseudo_spi_intf_scan_test.do		sys_pc_pseudo_spi_intf_scan_test.do
sys_pc_read_wrt_sram_test.do		sys_pc_read_wrt_sram_test.do
sys_pc_read_wrt_sram_vg_test.do		sys_pc_read_wrt_sram_vg_test.do
sys_pc_wrt_sram_sum10_test.do		sys_pc_wrt_sram_sum10_test.do
sys_pc_wrt_sram_sum10_vg_test.do		sys_pc_wrt_sram_sum10_vg_test.do
sys_pseudo_spi_intf_scan_bug_test.do		sys_pseudo_spi_intf_scan_bug_test.do
sys_pseudo_spi_intf_scan_fpga_test.do		sys_pseudo_spi_intf_scan_fpga_test.do
sys_pseudo_spi_intf_scan_test.do		sys_pseudo_spi_intf_scan_test.do
sys_pseudo_spi_intf_scan_vg_test.do		sys_pseudo_spi_intf_scan_vg_test.do
sys_pseudo_spi_intf_scan_vg_test_bug.do		sys_pseudo_spi_intf_scan_vg_test_bug.do
sys_pseudo_spi_intf_scan_vg_test_cct.do		sys_pseudo_spi_intf_scan_vg_test_cct.do
sys_pseudo_spi_intf_scan_vg_test_cpu.do		sys_pseudo_spi_intf_scan_vg_test_cpu.do
sys_pseudo_spi_intf_scan_vg_test_spi.do		sys_pseudo_spi_intf_scan_vg_test_spi.do
sys_pseudo_spi_intf_scan_vga_test.do		sys_pseudo_spi_intf_scan_vga_test.do
sys_share_superalu_cordic_test.do		sys_share_superalu_cordic_test.do
sys_share_superalu_mult_test.do		sys_share_superalu_mult_test.do
temp.txt		temp.txt
temp.xlsx		temp.xlsx
test_result.txt		test_result.txt
vsim.wlf		vsim.wlf
vsim_022817_2303.log		vsim_022817_2303.log
vsim_040717_0111.log		vsim_040717_0111.log
vsim_041917_0156.log		vsim_041917_0156.log
vsim_042017_0120.log		vsim_042017_0120.log