This repository contains source code for a VHDL implementation of the high-precision integer division algorithm using a two-level hardware structure proposed in the paper "High-Precision Priority Encoder Based Integer Division Algorithm." All components are generalized such that only generics need modified to adapt the hardware to different bit precisions.
- For implementation and on-board testing, all files in
/srcand subdirectories are required.- Technically, not all of the small encoder components in
/src/Base Encodersare needed depending on bit precision, but if you are switching between bit precisions it is recommended to simply import all of them, aspriority_encoder_genericwill only instantiate the necessary components. - To adjust for different bit precisions, modify the generics in the top-level file.
- Constraint files for Digilent Basys 3 and Nexys A7-100T FPGA development boards are located in
/src/XCVR. For other devices, adapt these constraints appropriately.
- Technically, not all of the small encoder components in
- For synthesis and simulation only, the files in
/src/XCVRare not required. Everything else is as stated above.
- Some useful resources for testing can be found here.
- The code provided implements our serial transceiver, which can be found here.
