+
+
+ PCB Layout Reference · Synchronous Buck
+ Where every part in the buck stage wants to sit
+ U_BUCK1 (TLV62569DBV) switches at ~2–3 MHz and delivers up to 2 A — placement determines whether it's quiet or noisy. This maps the schematic to a suggested top-copper floorplan you can model your PCB after.
+
+ Source: PCB/power_buck.kicad_sch
+ Nets: VSYS → 3V3
+ Package: SOT-23-5
+
+
+
+
+ What's on this sheet
+ Six parts, one power stage. Values as drawn in the schematic.
+
+
+
+
+ Suggested floorplan
+ Top copper layer, drawn roughly to scale. Trace weight signals current, not just wire — the input loop and switch node get thick, short, direct copper; the feedback path gets thin copper routed the long way around to stay quiet.
+
+
+
+ Top-layer placement and routing for U_BUCK1, sized roughly to real footprint proportions. Gold copper carries the input, switch, and output power path; pale blue carries the low-current FB and EN signals; rings mark vias dropping straight to the ground plane. Board edges shown are the crop of this local zone, not the full board.
+
+
+
+
+
+
+
+ Why it's arranged this way
+
+ A Input loop stays tiny. C_BUCK_IN1 sits directly on top of VIN, with its ground pad dropping straight to a via. VIN, the cap, and the return path form the loop the IC's fast input-current pulses actually flow through — keep its area small and this is one of the highest-leverage placements on the board for both efficiency and radiated noise.
B SW node is short and alone. The trace from pin 3 to L_BUCK1 carries the full switched current at the IC's switching frequency and acts as an antenna if it's long or fat. Keep it the shortest, most direct copper on the board and don't route anything else near or under it.
C Feedback taps the output cap, not the inductor. R_FB1 picks up VOUT right at C_BUCK_OUT1's pad — the point that's actually regulated — instead of further upstream where switching ripple is still settling.
D Every return pad gets its own via. C_BUCK_IN1, U_BUCK1, C_BUCK_OUT1, and R_FB2 each drop to the ground plane independently rather than daisy-chaining through each other on the top layer, so switching return current can't inject noise into the quiet feedback ground.
E FB takes the long way home. Once through the divider, the FB signal is thin and high-impedance — a few millivolts of coupled switching noise here shows up directly as output ripple. It's routed around the left side of the IC, clear of the SW/L1 copper, even though that's a longer path.
+
+
+
+ Routing order
+ If you're placing copper by hand, do it roughly in this order — later steps have less freedom once earlier ones are locked in.
+
+ Pour ground on the bottom layer first; treat everything else as carving space out of it.
+ Place U_BUCK1, then butt C_BUCK_IN1 against its VIN pin before anything else claims that space.
+ Route SW to L_BUCK1 — shortest path wins, width sized for 2 A.
+ Place C_BUCK_OUT1 off the inductor's far pad, then fan VOUT out to the load.
+ Tap FB at C_BUCK_OUT1, place R_FB1/R_FB2 close together, route the sense line back around the IC last — by now you know exactly what copper it has to avoid.
+ Stitch a via at every ground pad (C_IN, IC, C_OUT, R_FB2).
+
+
+
+
+ Worth double-checking: R_FB1/R_FB2 (100 kΩ / 56.2 kΩ) work out to roughly 1.67 V at the TLV62569's 0.6 V typical reference (VOUT = 0.6 × (1 + R_FB1⁄R_FB2)), not the 3.3 V implied by the "3V3" net label on that rail. Worth confirming which one is intended before you commit to this floorplan — it doesn't change the layout, but it's a five-minute check now versus a respin later.
+
+
+
+ Generated from PCB/power_buck.kicad_sch — a placement reference, not a manufacturing drawing. Model your actual footprints and DRC against your fab's rules.
+
+
+
+
+
+ PCB Layout Reference · Linear Li-ion Charger
+ The charger's whole story is thermal, not noise
+ U_CHG1 (BQ25185) is a linear charger — no inductor, no switch node. The layout problem isn't EMI, it's getting heat out of a 2×3mm WSON-10 package while keeping three separate power nets short. Values below are verified against TI's own datasheet, not estimated.
+
+ Source: PCB/power_charger.kicad_sch
+ Nets: VBUS → VSYS / VBAT
+ Package: WSON-10
+
+
+
+
+ What's on this sheet
+ Ten parts. Every setting resistor's effect is confirmed against the BQ25185 datasheet (SLUSF65A), not assumed.
+
+
+
+
+ Suggested floorplan
+ IN and the SYS/BAT pair sit on opposite edges of the package — a genuine gift from the pinout. Route VBUS straight through from one side to SYS/VBAT on the other and nothing has to double back.
+
+
+
+ Top-layer placement for U_CHG1. Gold copper carries VBUS/VSYS/VBAT power; pale blue carries the low-current setting and status signals; rings mark vias to the ground plane. IN sits on the right, SYS/BAT on the left — route the power path straight through rather than doubling back.
+
+
+
+
+
+
+
+ Why it's arranged this way
+
+ A The thermal pad is the real story here. This is a linear charger — every volt it drops between IN/SYS/BAT and whatever it's not dropping across the battery becomes heat inside a 2×3mm package. TI's WSON layout guidance calls for 4–6 vias under the pad at ≤0.3mm diameter, ~1mm spacing; the stock footprint in this library only places 2. Add the rest before fab.
B IN, SYS, and BAT each get their own decoupling, right at their own pin. TI's datasheet layout guidelines (§8.4.1) say it plainly: place the IN, SYS, and BAT capacitors as close as possible to the device — these are three separate short loops, not one shared input loop like a switcher would have.
C VBUS in on the right, VSYS out on the left — no doubling back. The package puts IN on one edge and SYS/BAT on the opposite edge. That's not a layout choice, it's a gift from the pinout: route the power path straight through and every trace is as short as it can be.
D ISET especially wants a short, direct trace. R_ISET1 sets the actual charge current (ICHG = KISET /RISET , K≈300AΩ) — at 600Ω that's ≈500mA, matching TI's own tested value for this exact resistance. Stray resistance or noise pickup on this trace shows up directly as charge-current error.
E GND pin and thermal pad share one solid pour. TI's guideline is explicit: "a solid ground plane tied to the GND pin and thermal pad should be used" — not two separate ground fills stitched together, one plane doing both jobs.
+
+
+
+ Routing priority
+ Do it roughly in this order — the thermal pad and its via array need the most freedom, so give them first pick of the copper underneath the part.
+
+ Place U_CHG1, then lay out the thermal-pad via array before anything else claims that space (aim for 4–6 vias, not the footprint's stock 2).
+ Butt C_VIN_1/C_VIN_2 against the IN pin, C_SYS_1/C_SYS_2 against SYS, and C_BAT1 against BAT — three independent short loops.
+ Route VBUS in from one edge and VSYS/VBAT out the opposite edge, straight through.
+ Cluster R_ISET1, R_VSET1, and R_TS1 tight against their pins on the analog side — keep them clear of the power copper.
+ Pour ground last, tying the GND pin, the thermal pad array, and every decoupling cap's return into one plane.
+
+
+
+
+ Verified against TI datasheet SLUSF65A: R_ISET1 (600Ω) → ICHG ≈ 500mA is one of TI's own named test conditions, not an estimate. R_VSET1 (18kΩ) maps to Table 7-1 exactly: 500mA input current limit, 4.2V battery regulation, 3.0V precharge threshold — standard single-cell Li-ion settings. R_TS1 (10kΩ) matches TI's own instruction verbatim: "if the TS function is not required, connect a 10kΩ resistor from the TS/MR pin to GND." Nothing on this sheet needed correcting.
+
+
+
+ Generated from PCB/power_charger.kicad_sch — a placement reference, not a manufacturing drawing. Model your actual footprints and DRC against your fab's rules.
+
+
+
+
+
+ PCB Layout Reference · Soft-Latch Power Switch
+ Half of this circuit is electrical, half is where your thumb goes
+ Q_PWR1 carries the entire board's current — every milliamp the ESP32, XBee, OLED, and everything else draws passes through one SOT-23 PMOS. But the layout-driving constraint here isn't electrical at all: SW_PWR1 is a physical button that has to land under a hole in your enclosure.
+
+ Source: PCB/power_control.kicad_sch
+ Nets: VSYS → PWR_EN
+ Package: SOT-23 ×2, SOD-123 ×2
+
+
+
+
+ What's on this sheet
+ A press-to-start, software-held latch: the button turns the board on, the MCU has to grab the hold line before the button is released, and either side of a diode-OR can keep power on.
+
+
+
+
+ Suggested floorplan
+ Top copper layer. The VSYS→PWR_EN path runs straight across the top as one thick lane; the latch logic hangs underneath it as a compact, low-current block; the button sits wherever your enclosure needs it to.
+
+
+
+ Top-layer placement for the soft-latch switch. Gold copper is the VSYS→PWR_EN power path; pale blue is the low-current gate-drive, sense, and control logic; rings mark vias to the ground plane.
+
+
+
+
+
+
+
+ Why it's arranged this way
+
+ A Q_PWR1 is the one part on this sheet that isn't low-current. Every downstream milliamp — MCU, XBee, OLED, everything — flows through its source-drain path. DMG2305UX's RDS(on) (~35–50mΩ) keeps drop and heat trivial at this board's current budget, but a SOT-23 has no separate thermal pad — the source/drain copper itself is the heatsink, so give those pads real copper, not just a skinny trace.
B SW_PWR1's position isn't yours to optimize electrically. It has to land under a hole in whatever enclosure this board sits in — mechanical placement drives this part, and the rest of the latch logic has to route to wherever that ends up, not the other way around.
C C_DBNC1 sits right on the switch's own pins. Same principle as the charger's pushbutton guidance in its own datasheet: the debounce cap does its job by being close to the contact bounce it's filtering, not by being close to anything else.
D The diode-OR and its pull-down are one compact decision node. D_OR1, D_OR2, R_LATCH_G1, and Q_LATCH1's gate all meet at PWR_LATCH_G — keeping that cluster tight matters less for noise than for just keeping the logic legible on the board.
E PWR_HOLD arriving late is a hard failure, not a glitch. Per this project's own GPIO notes, pin 36 (PWR_HOLD) must go high as the MCU's very first instruction — release the button before that happens and R_LATCH_G1's pull-down turns everything back off. Not a layout fix, but it's the reason D_OR2's path exists at all.
+
+
+
+ Routing priority
+ The button's position is fixed by the enclosure before you start — everything else routes around it.
+
+ Place SW_PWR1 wherever the enclosure cutout requires; that position is a constraint, not a choice.
+ Put C_DBNC1 directly on SW_PWR1's sense pin before routing anything else nearby.
+ Route the VSYS→Q_PWR1→PWR_EN lane as one straight, generously-wide path across the board.
+ Cluster Q_LATCH1, R_GATE1, R_LATCH_G1, D_OR1, and D_OR2 into one compact low-current block under the main lane.
+ Bring PWR_BTN_SENSE and PWR_HOLD in from wherever the MCU sheet actually sits — these are off-sheet nets, not local components.
+
+
+
+
+ Checked, not just assumed: DMG2305UX is rated for ~4A continuous with 35–50mΩ RDS(on) in this SOT-23 package — comfortably oversized for a handheld controller's sub-2A system budget, so this isn't a thermal risk the way the charger's WSON is. Nothing on this sheet needed correcting.
+
+
+
+ Generated from PCB/power_control.kicad_sch — a placement reference, not a manufacturing drawing. Model your actual footprints and DRC against your fab's rules.
+
+
+