diff --git a/integration_tests/MODULE_INST/module_inst.va b/integration_tests/MODULE_INST/module_inst.va new file mode 100644 index 000000000..d628075df --- /dev/null +++ b/integration_tests/MODULE_INST/module_inst.va @@ -0,0 +1,35 @@ +// Test module instantiation syntax support +// This tests hierarchical module instantiation with parameter overrides + +`include "constants.vams" +`include "disciplines.vams" + +// Simple resistor module that can be instantiated +module resistor(p, n); + inout p, n; + electrical p, n; + parameter real r = 1.0 from (0:inf); + + analog begin + I(p, n) <+ V(p, n) / r; + end +endmodule + +// Module that instantiates resistors +module module_inst(d, s); + inout d, s; + electrical d, s, mid; + + parameter real rwire = 1e-3 from (0:inf); + parameter real rload = 1e3 from (0:inf); + + // Module instantiation with parameter override + resistor #(.r(rwire)) r_wire (d, mid); + resistor #(.r(rload)) r_load (mid, s); + + // Additional behavior + analog begin + // Add small leakage current + I(d, s) <+ V(d, s) * 1e-12; + end +endmodule diff --git a/openvaf/hir_def/src/item_tree.rs b/openvaf/hir_def/src/item_tree.rs index b40a07c4a..8ceb36137 100644 --- a/openvaf/hir_def/src/item_tree.rs +++ b/openvaf/hir_def/src/item_tree.rs @@ -73,6 +73,7 @@ impl ItemTree { ports, branches, functions, + module_insts, } = &mut self.data; modules.shrink_to_fit(); disciplines.shrink_to_fit(); @@ -87,6 +88,7 @@ impl ItemTree { functions.shrink_to_fit(); nature_attrs.shrink_to_fit(); discipline_attrs.shrink_to_fit(); + module_insts.shrink_to_fit(); } pub fn block_scope(&self, block: AstId) -> &Block { @@ -109,6 +111,7 @@ pub struct ItemTreeData { pub ports: Arena, pub branches: Arena, pub functions: Arena, + pub module_insts: Arena, } /// Trait implemented by all item nodes in the item tree. @@ -230,6 +233,7 @@ item_tree_nodes! { Function in functions -> ast::Function, NatureAttr in nature_attrs -> ast::NatureAttr, DisciplineAttr in discipline_attrs -> ast::DisciplineAttr, + ModuleInstItem in module_insts -> ast::ModuleInst, } #[derive(Debug, Eq, PartialEq, Clone)] @@ -250,6 +254,7 @@ pub enum ModuleItem { Branch(ItemTreeId), Node(LocalNodeId), Function(ItemTreeId), + ModuleInst(ItemTreeId), } impl_from_typed! ( @@ -259,7 +264,8 @@ impl_from_typed! ( Variable(ItemTreeId), Branch(ItemTreeId), Node(LocalNodeId), - Function(ItemTreeId) for ModuleItem + Function(ItemTreeId), + ModuleInst(ItemTreeId) for ModuleItem ); #[derive(Debug, Eq, PartialEq, Clone)] @@ -418,6 +424,22 @@ impl_from_typed! ( FunctionArg(LocalFunctionArgId) for FunctionItem ); +/// A module instantiation (hierarchical instance) +/// Example: `resistor #(.r(rwire)) r1 (d, de0);` +#[derive(Debug, Eq, PartialEq, Clone)] +pub struct ModuleInstItem { + /// Instance name (e.g., "r1") + pub name: Name, + /// Module type being instantiated (e.g., "resistor") + pub module_name: Name, + /// Parameter overrides (e.g., [("r", "rwire")]) + pub param_assignments: Vec<(Name, Name)>, + /// Port connections (node names in order) + pub port_connections: Vec, + /// AST node reference + pub ast_id: AstId, +} + #[derive(Debug, Eq, PartialEq, Clone)] pub struct FunctionArg { pub name: Name, diff --git a/openvaf/hir_def/src/item_tree/lower.rs b/openvaf/hir_def/src/item_tree/lower.rs index 05e5e6685..434e3da04 100644 --- a/openvaf/hir_def/src/item_tree/lower.rs +++ b/openvaf/hir_def/src/item_tree/lower.rs @@ -11,8 +11,8 @@ use typed_index_collections::TiVec; use super::{ Block, Branch, BranchKind, Discipline, DisciplineAttr, DisciplineAttrKind, Domain, Function, - FunctionArg, FunctionItem, ItemTree, ItemTreeId, Module, ModuleItem, Nature, NatureAttr, - NatureRef, NatureRefKind, Net, Node, Param, Port, RootItem, Var, + FunctionArg, FunctionItem, ItemTree, ItemTreeId, Module, ModuleInstItem, ModuleItem, Nature, + NatureAttr, NatureRef, NatureRefKind, Net, Node, Param, Port, RootItem, Var, }; // use tracing::trace; use crate::db::HirDefDB; @@ -300,6 +300,7 @@ impl Ctx { } ast::ModuleItem::BranchDecl(branch) => self.lower_branch(branch, dst), ast::ModuleItem::AliasParam(alias) => self.lower_alias_param(alias, dst), + ast::ModuleItem::ModuleInst(inst) => self.lower_module_inst(inst, dst), }; } } @@ -610,4 +611,59 @@ impl Ctx { dst.push(param.into()) } } + + fn lower_module_inst(&mut self, inst: ast::ModuleInst, dst: &mut Vec) { + let inst_name = match inst.inst_name() { + Some(name) => name.as_name(), + None => return, + }; + let module_name = match inst.module_name() { + Some(name) => name.as_name(), + None => return, + }; + + // Extract parameter assignments: .param(value) -> (param_name, value_expr_as_name) + let param_assignments = inst + .param_assignments() + .map(|pas| { + pas.param_assignments() + .filter_map(|pa| { + let param_name = pa.param()?.as_name(); + // Try to extract the value as a simple name/identifier + // For complex expressions, we just skip for now + let value_name = pa.value().and_then(|e| e.as_ident())?; + Some((param_name, value_name)) + }) + .collect() + }) + .unwrap_or_default(); + + // Extract port connections - for positional connections, extract the node name + let port_connections = inst + .port_connections() + .map(|pcs| { + pcs.port_connections() + .filter_map(|pc| { + // For named connections: .port(expr) - use the connection expr + // For positional connections: just expr - use the expr + let expr = + if pc.dot_token().is_some() { pc.connection() } else { pc.expr() }; + expr.and_then(|e| e.as_ident()) + }) + .collect() + }) + .unwrap_or_default(); + + let ast_id = self.source_ast_id_map.ast_id(&inst); + + let module_inst = ModuleInstItem { + name: inst_name, + module_name, + param_assignments, + port_connections, + ast_id, + }; + let id = self.tree.data.module_insts.push_and_get_key(module_inst); + dst.push(id.into()); + } } diff --git a/openvaf/hir_def/src/item_tree/pretty.rs b/openvaf/hir_def/src/item_tree/pretty.rs index 5bbc4590d..fa71dc835 100644 --- a/openvaf/hir_def/src/item_tree/pretty.rs +++ b/openvaf/hir_def/src/item_tree/pretty.rs @@ -124,6 +124,17 @@ impl<'a> Printer<'a> { let param = &self.tree[param]; wln!(self, "aliasparam {} = {:?}", param.name, param.src); } + ModuleItem::ModuleInst(inst) => { + let inst = &self.tree[inst]; + wln!( + self, + "module_inst {} {} #({:?}) ({:?})", + inst.module_name, + inst.name, + inst.param_assignments, + inst.port_connections + ); + } } } } diff --git a/openvaf/hir_def/src/nameres/collect.rs b/openvaf/hir_def/src/nameres/collect.rs index 320586cf2..c368c8aaf 100644 --- a/openvaf/hir_def/src/nameres/collect.rs +++ b/openvaf/hir_def/src/nameres/collect.rs @@ -282,6 +282,10 @@ impl DefCollector<'_> { ModuleItem::AliasParameter(id) => { self.insert_item_decl(scope, self.tree[id].name.clone(), id) } + ModuleItem::ModuleInst(_) => { + // Module instances are recorded but don't participate in name resolution + // They will be processed later during elaboration/flattening + } } } } diff --git a/openvaf/parser/src/grammar/items/module.rs b/openvaf/parser/src/grammar/items/module.rs index 3ca4e2304..3483a5227 100644 --- a/openvaf/parser/src/grammar/items/module.rs +++ b/openvaf/parser/src/grammar/items/module.rs @@ -120,7 +120,15 @@ fn module_items(p: &mut Parser) { net_decl::(p, m); } IDENT => { - net_decl::(p, m); + // Distinguish between net declaration and module instantiation: + // Net declaration: `discipline name, name2;` - IDENT followed by IDENT, comma, or semicolon + // Module instantiation: `module_name #(params) inst_name (ports);` or `module_name inst_name (ports);` + // Key distinction: module inst has IDENT followed by #( or IDENT followed by IDENT then ( + if p.nth(1) == POUND || (p.nth(1) == IDENT && p.nth(2) == L_PAREN) { + module_inst(p, m); + } else { + net_decl::(p, m); + } } PARAMETER_KW | LOCALPARAM_KW => { parameter_decl(p, m); @@ -232,3 +240,89 @@ fn branch_decl(p: &mut Parser, m: Marker) { p.eat(T![;]); m.complete(p, BRANCH_DECL); } + +/// Parse module instantiation: `module_name #(.param(value), ...) instance_name (port1, port2, ...);` +/// Example: `resistor #(.r(rwire)) r1 (d, de0);` +fn module_inst(p: &mut Parser, m: Marker) { + // Module name (the type being instantiated) + name_ref_r(p, TokenSet::new(&[POUND, IDENT])); + + // Optional parameter assignments: #(.param(value), ...) + if p.at(POUND) { + param_assignments(p); + } + + // Instance name + name_r(p, TokenSet::new(&[T!['('], T![;]])); + + // Port connections: (port1, port2, ...) or (.port(connection), ...) + if p.at(T!['(']) { + port_connections(p); + } else { + p.error(p.unexpected_token_msg(T!['('])); + } + + p.eat(T![;]); + m.complete(p, MODULE_INST); +} + +/// Parse parameter assignments: #(.param(value), ...) +fn param_assignments(p: &mut Parser) { + let m = p.start(); + p.bump(POUND); + p.expect(T!['(']); + + if !p.at(T![')']) { + param_assignment(p); + while p.eat(T![,]) { + param_assignment(p); + } + } + + p.expect(T![')']); + m.complete(p, PARAM_ASSIGNMENTS); +} + +/// Parse a single parameter assignment: .param(value) +fn param_assignment(p: &mut Parser) { + let m = p.start(); + p.expect(T![.]); + name_r(p, TokenSet::new(&[T!['(']])); + p.expect(T!['(']); + expr(p); + p.expect(T![')']); + m.complete(p, PARAM_ASSIGNMENT); +} + +/// Parse port connections: (expr, expr, ...) or (.port(expr), ...) +fn port_connections(p: &mut Parser) { + let m = p.start(); + p.bump(T!['(']); + + if !p.at(T![')']) { + port_connection(p); + while p.eat(T![,]) { + port_connection(p); + } + } + + p.expect(T![')']); + m.complete(p, PORT_CONNECTIONS); +} + +/// Parse a single port connection: either positional (expr) or named (.port(expr)) +fn port_connection(p: &mut Parser) { + let m = p.start(); + if p.at(T![.]) { + // Named port connection: .port(expr) + p.bump(T![.]); + name_r(p, TokenSet::new(&[T!['(']])); + p.expect(T!['(']); + expr(p); + p.expect(T![')']); + } else { + // Positional port connection: just an expression (usually a name) + expr(p); + } + m.complete(p, PORT_CONNECTION); +} diff --git a/openvaf/syntax/src/ast/generated/nodes.rs b/openvaf/syntax/src/ast/generated/nodes.rs index cc2f471da..a47e89fb5 100644 --- a/openvaf/syntax/src/ast/generated/nodes.rs +++ b/openvaf/syntax/src/ast/generated/nodes.rs @@ -459,6 +459,18 @@ impl AliasParam { pub fn semicolon_token(&self) -> Option { support::token(&self.syntax, T![;]) } } #[derive(Debug, Clone, PartialEq, Eq, Hash)] +pub struct ModuleInst { + pub(crate) syntax: SyntaxNode, +} +impl ast::AttrsOwner for ModuleInst {} +impl ModuleInst { + pub fn module_name(&self) -> Option { support::child(&self.syntax) } + pub fn param_assignments(&self) -> Option { support::child(&self.syntax) } + pub fn inst_name(&self) -> Option { support::child(&self.syntax) } + pub fn port_connections(&self) -> Option { support::child(&self.syntax) } + pub fn semicolon_token(&self) -> Option { support::token(&self.syntax, T![;]) } +} +#[derive(Debug, Clone, PartialEq, Eq, Hash)] pub struct ModulePort { pub(crate) syntax: SyntaxNode, } @@ -536,6 +548,52 @@ impl FunctionArg { pub fn semicolon_token(&self) -> Option { support::token(&self.syntax, T![;]) } } #[derive(Debug, Clone, PartialEq, Eq, Hash)] +pub struct ParamAssignments { + pub(crate) syntax: SyntaxNode, +} +impl ParamAssignments { + pub fn pound_token(&self) -> Option { support::token(&self.syntax, T![#]) } + pub fn l_paren_token(&self) -> Option { support::token(&self.syntax, T!['(']) } + pub fn param_assignments(&self) -> AstChildren { + support::children(&self.syntax) + } + pub fn r_paren_token(&self) -> Option { support::token(&self.syntax, T![')']) } +} +#[derive(Debug, Clone, PartialEq, Eq, Hash)] +pub struct PortConnections { + pub(crate) syntax: SyntaxNode, +} +impl PortConnections { + pub fn l_paren_token(&self) -> Option { support::token(&self.syntax, T!['(']) } + pub fn port_connections(&self) -> AstChildren { + support::children(&self.syntax) + } + pub fn r_paren_token(&self) -> Option { support::token(&self.syntax, T![')']) } +} +#[derive(Debug, Clone, PartialEq, Eq, Hash)] +pub struct ParamAssignment { + pub(crate) syntax: SyntaxNode, +} +impl ParamAssignment { + pub fn dot_token(&self) -> Option { support::token(&self.syntax, T![.]) } + pub fn param(&self) -> Option { support::child(&self.syntax) } + pub fn l_paren_token(&self) -> Option { support::token(&self.syntax, T!['(']) } + pub fn value(&self) -> Option { support::child(&self.syntax) } + pub fn r_paren_token(&self) -> Option { support::token(&self.syntax, T![')']) } +} +#[derive(Debug, Clone, PartialEq, Eq, Hash)] +pub struct PortConnection { + pub(crate) syntax: SyntaxNode, +} +impl PortConnection { + pub fn expr(&self) -> Option { support::child(&self.syntax) } + pub fn dot_token(&self) -> Option { support::token(&self.syntax, T![.]) } + pub fn port(&self) -> Option { support::child(&self.syntax) } + pub fn l_paren_token(&self) -> Option { support::token(&self.syntax, T!['(']) } + pub fn connection(&self) -> Option { support::child(&self.syntax) } + pub fn r_paren_token(&self) -> Option { support::token(&self.syntax, T![')']) } +} +#[derive(Debug, Clone, PartialEq, Eq, Hash)] pub enum Expr { PrefixExpr(PrefixExpr), BinExpr(BinExpr), @@ -589,6 +647,7 @@ pub enum ModuleItem { VarDecl(VarDecl), ParamDecl(ParamDecl), AliasParam(AliasParam), + ModuleInst(ModuleInst), } #[derive(Debug, Clone, PartialEq, Eq, Hash)] pub enum ModulePortKind { @@ -1092,6 +1151,17 @@ impl AstNode for AliasParam { } fn syntax(&self) -> &SyntaxNode { &self.syntax } } +impl AstNode for ModuleInst { + fn can_cast(kind: SyntaxKind) -> bool { kind == MODULE_INST } + fn cast(syntax: SyntaxNode) -> Option { + if Self::can_cast(syntax.kind()) { + Some(Self { syntax }) + } else { + None + } + } + fn syntax(&self) -> &SyntaxNode { &self.syntax } +} impl AstNode for ModulePort { fn can_cast(kind: SyntaxKind) -> bool { kind == MODULE_PORT } fn cast(syntax: SyntaxNode) -> Option { @@ -1180,6 +1250,50 @@ impl AstNode for FunctionArg { } fn syntax(&self) -> &SyntaxNode { &self.syntax } } +impl AstNode for ParamAssignments { + fn can_cast(kind: SyntaxKind) -> bool { kind == PARAM_ASSIGNMENTS } + fn cast(syntax: SyntaxNode) -> Option { + if Self::can_cast(syntax.kind()) { + Some(Self { syntax }) + } else { + None + } + } + fn syntax(&self) -> &SyntaxNode { &self.syntax } +} +impl AstNode for PortConnections { + fn can_cast(kind: SyntaxKind) -> bool { kind == PORT_CONNECTIONS } + fn cast(syntax: SyntaxNode) -> Option { + if Self::can_cast(syntax.kind()) { + Some(Self { syntax }) + } else { + None + } + } + fn syntax(&self) -> &SyntaxNode { &self.syntax } +} +impl AstNode for ParamAssignment { + fn can_cast(kind: SyntaxKind) -> bool { kind == PARAM_ASSIGNMENT } + fn cast(syntax: SyntaxNode) -> Option { + if Self::can_cast(syntax.kind()) { + Some(Self { syntax }) + } else { + None + } + } + fn syntax(&self) -> &SyntaxNode { &self.syntax } +} +impl AstNode for PortConnection { + fn can_cast(kind: SyntaxKind) -> bool { kind == PORT_CONNECTION } + fn cast(syntax: SyntaxNode) -> Option { + if Self::can_cast(syntax.kind()) { + Some(Self { syntax }) + } else { + None + } + } + fn syntax(&self) -> &SyntaxNode { &self.syntax } +} impl From for Expr { fn from(node: PrefixExpr) -> Expr { Expr::PrefixExpr(node) } } @@ -1424,11 +1538,14 @@ impl From for ModuleItem { impl From for ModuleItem { fn from(node: AliasParam) -> ModuleItem { ModuleItem::AliasParam(node) } } +impl From for ModuleItem { + fn from(node: ModuleInst) -> ModuleItem { ModuleItem::ModuleInst(node) } +} impl AstNode for ModuleItem { fn can_cast(kind: SyntaxKind) -> bool { match kind { BODY_PORT_DECL | NET_DECL | ANALOG_BEHAVIOUR | FUNCTION | BRANCH_DECL | VAR_DECL - | PARAM_DECL | ALIAS_PARAM => true, + | PARAM_DECL | ALIAS_PARAM | MODULE_INST => true, _ => false, } } @@ -1442,6 +1559,7 @@ impl AstNode for ModuleItem { VAR_DECL => ModuleItem::VarDecl(VarDecl { syntax }), PARAM_DECL => ModuleItem::ParamDecl(ParamDecl { syntax }), ALIAS_PARAM => ModuleItem::AliasParam(AliasParam { syntax }), + MODULE_INST => ModuleItem::ModuleInst(ModuleInst { syntax }), _ => return None, }; Some(res) @@ -1456,6 +1574,7 @@ impl AstNode for ModuleItem { ModuleItem::VarDecl(it) => &it.syntax, ModuleItem::ParamDecl(it) => &it.syntax, ModuleItem::AliasParam(it) => &it.syntax, + ModuleItem::ModuleInst(it) => &it.syntax, } } } @@ -1817,6 +1936,11 @@ impl std::fmt::Display for AliasParam { std::fmt::Display::fmt(self.syntax(), f) } } +impl std::fmt::Display for ModuleInst { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} impl std::fmt::Display for ModulePort { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { std::fmt::Display::fmt(self.syntax(), f) @@ -1857,3 +1981,23 @@ impl std::fmt::Display for FunctionArg { std::fmt::Display::fmt(self.syntax(), f) } } +impl std::fmt::Display for ParamAssignments { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} +impl std::fmt::Display for PortConnections { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} +impl std::fmt::Display for ParamAssignment { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} +impl std::fmt::Display for PortConnection { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + std::fmt::Display::fmt(self.syntax(), f) + } +} diff --git a/openvaf/syntax/veriloga.ungram b/openvaf/syntax/veriloga.ungram index 0fccf808d..6ab9383b9 100644 --- a/openvaf/syntax/veriloga.ungram +++ b/openvaf/syntax/veriloga.ungram @@ -195,6 +195,7 @@ ModuleItem = | VarDecl | ParamDecl | AliasParam +| ModuleInst ModulePorts = '('ports: (ModulePort (',' ModulePort)*)? ')' ModulePort = kind: ModulePortKind @@ -257,3 +258,20 @@ FunctionArg = BranchDecl = AttrList* 'branch' ArgList (Name (',' Name)*)';' + +// Module instantiation: module_name #(.param(value), ...) instance_name (port1, port2, ...); +// Example: resistor #(.r(rwire)) r1 (d, de0); +ModuleInst = + AttrList* module_name:NameRef ParamAssignments? inst_name:Name PortConnections ';' + +ParamAssignments = + '#' '(' (ParamAssignment (',' ParamAssignment)*)? ')' + +ParamAssignment = + '.' param:Name '(' value:Expr ')' + +PortConnections = + '(' (PortConnection (',' PortConnection)*)? ')' + +PortConnection = + Expr | '.' port:Name '(' connection:Expr ')' diff --git a/openvaf/test_data/item_tree/module_inst.def_map b/openvaf/test_data/item_tree/module_inst.def_map new file mode 100644 index 000000000..b988341b1 --- /dev/null +++ b/openvaf/test_data/item_tree/module_inst.def_map @@ -0,0 +1,13 @@ +test = module; + + $angle = hierarchical parameter system function; + $hflip = hierarchical parameter system function; + $mfactor = hierarchical parameter system function; + $vflip = hierarchical parameter system function; + $xposition = hierarchical parameter system function; + $yposition = hierarchical parameter system function; + a = node; + b = node; + mid = node; + r1 = parameter; + r2 = parameter; diff --git a/openvaf/test_data/item_tree/module_inst.item_tree b/openvaf/test_data/item_tree/module_inst.item_tree new file mode 100644 index 000000000..85dc5c860 --- /dev/null +++ b/openvaf/test_data/item_tree/module_inst.item_tree @@ -0,0 +1,9 @@ +module test + + node a = {is_input: true, is_output:true, gnd: false , discipline Some(Name("electrical"))} + node b = {is_input: true, is_output:true, gnd: false , discipline Some(Name("electrical"))} + node mid = {is_input: false, is_output:false, gnd: false , discipline Some(Name("electrical"))} + param real r1 + param real r2 + module_inst resistor inst1 #([(Name("r"), Name("r1"))]) ([Name("a"), Name("mid")]) + module_inst resistor inst2 #([(Name("r"), Name("r2"))]) ([Name("mid"), Name("b")]) \ No newline at end of file diff --git a/openvaf/test_data/item_tree/module_inst.va b/openvaf/test_data/item_tree/module_inst.va new file mode 100644 index 000000000..8660d7479 --- /dev/null +++ b/openvaf/test_data/item_tree/module_inst.va @@ -0,0 +1,15 @@ +// Test module instantiation parsing +module test(a, b); + electrical a, b, mid; + inout a, b; + + parameter real r1 = 100.0; + parameter real r2 = 200.0; + + // Module instantiation with parameter override + resistor #(.r(r1)) inst1 (a, mid); + + // Module instantiation with multiple parameters + resistor #(.r(r2)) inst2 (mid, b); + +endmodule diff --git a/openvaf/tokens/src/parser/generated.rs b/openvaf/tokens/src/parser/generated.rs index 0a59b3ad8..abfc5d440 100644 --- a/openvaf/tokens/src/parser/generated.rs +++ b/openvaf/tokens/src/parser/generated.rs @@ -127,6 +127,7 @@ pub enum SyntaxKind { IF_STMT, LITERAL, MODULE_DECL, + MODULE_INST, MODULE_PORT, MODULE_PORTS, NAME, @@ -138,11 +139,15 @@ pub enum SyntaxKind { NET_DECL, NETS, PARAM, + PARAM_ASSIGNMENT, + PARAM_ASSIGNMENTS, ALIAS_PARAM, PARAM_DECL, PAREN_EXPR, PATH, PATH_EXPR, + PORT_CONNECTION, + PORT_CONNECTIONS, PORT_DECL, PORTS, PREFIX_EXPR, diff --git a/sourcegen/src/ast/src.rs b/sourcegen/src/ast/src.rs index c1880e2c3..fd0a25c80 100644 --- a/sourcegen/src/ast/src.rs +++ b/sourcegen/src/ast/src.rs @@ -126,6 +126,7 @@ pub(crate) const KINDS_SRC: KindsSrc = KindsSrc { "IF_STMT", "LITERAL", "MODULE_DECL", + "MODULE_INST", "MODULE_PORT", "MODULE_PORTS", "NAME", @@ -137,11 +138,15 @@ pub(crate) const KINDS_SRC: KindsSrc = KindsSrc { "NET_DECL", "NETS", "PARAM", + "PARAM_ASSIGNMENT", + "PARAM_ASSIGNMENTS", "ALIAS_PARAM", "PARAM_DECL", "PAREN_EXPR", "PATH", "PATH_EXPR", + "PORT_CONNECTION", + "PORT_CONNECTIONS", "PORT_DECL", "PORTS", "PREFIX_EXPR",