From fe87e961d769598d52ed8946854ba7a83d6df661 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 21 Sep 2025 10:09:28 +0300 Subject: [PATCH 01/37] BACKPORT: arm64: dts: qcom: qcs8300: add refgen regulator Add the refgen regulator block. It should be used for DSI controllers once they are added. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250921-refgen-v1-12-9d93e64133ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 2c9e4d7c6896ef285e884f0abf5c15d198cea469) [rsalveti: applied to monaco.dtsi, as the rename to qcs8300.dtsi is not part of this branch; the dt-bindings/thermal/thermal.h include the upstream commit adds is already present] Signed-off-by: Ricardo Salveti --- arch/arm64/boot/dts/qcom/monaco.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index d944da523804..edc426d4962d 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4922,6 +4922,12 @@ status = "disabled"; }; + refgen: regulator@891c000 { + compatible = "qcom,qcs8300-refgen-regulator", + "qcom,sm8250-refgen-regulator"; + reg = <0x0 0x0891c000 0x0 0x84>; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-623.0", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, From 1a71a93bade2f6b64c9ada38ebb291d777433a63 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Fri, 13 Mar 2026 10:38:16 +0000 Subject: [PATCH 02/37] UPSTREAM: arm64: dts: qcom: monaco: Add HS/SS endpoints for USB1 controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a port node exposing the High‑Speed and Super‑Speed endpoints, allowing the USB controller to be linked through the device‑tree graph. Signed-off-by: Loic Poulain Signed-off-by: Srinivas Kandagatla Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260313103824.2634519-2-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 7ceeb30c33ce1e33cfc4087e8370df4801ce82bd) Signed-off-by: Ricardo Salveti --- arch/arm64/boot/dts/qcom/monaco.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index edc426d4962d..1e5025cbdcd6 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -5261,6 +5261,25 @@ wakeup-source; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + }; + }; + }; }; usb_2: usb@a400000 { From 893081e96d2dfd55c8f24d877f60744e9aae66ef Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 13 Mar 2026 10:38:17 +0000 Subject: [PATCH 03/37] UPSTREAM: arm64: dts: qcom: monaco: Add missing usb-role-switch property Add missing usb-role-switch property to usb controller node. Signed-off-by: Srinivas Kandagatla Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260313103824.2634519-3-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 2f5a32f4488ea9ea9ce50d0946ab88cf86e8b3b8) Signed-off-by: Ricardo Salveti --- arch/arm64/boot/dts/qcom/monaco.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 1e5025cbdcd6..adf49d44a57f 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -5258,6 +5258,7 @@ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; + usb-role-switch; wakeup-source; status = "disabled"; From 08bffc24e094a4cb441dcd87d94f0575800b1996 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:56 +0200 Subject: [PATCH 04/37] FROMGIT: arm64: dts: qcom: monaco: Fix the PCIe iommu-map entries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 46a7c01e7e9d ("arm64: dts: qcom: qcs8300: enable pcie0") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-15-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 2e455d9278550c8886a94e30a906437a26c79581) Signed-off-by: Ricardo Salveti --- arch/arm64/boot/dts/qcom/monaco.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index adf49d44a57f..5d34d287fc2e 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2394,8 +2394,8 @@ interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>, + <0x100 &pcie_smmu 0x0001 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>, <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; @@ -2569,8 +2569,8 @@ &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, - <0x100 &pcie_smmu 0x0081 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0080 0x0 0x1>, + <0x100 &pcie_smmu 0x0081 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; From 6a0291183fc9551461282bb2e6e0802a0a411011 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:58 +0200 Subject: [PATCH 05/37] FROMGIT: arm64: dts: qcom: monaco-evk-ifp-mezzanine: Fix the PCIe iommu-map entries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 5a67924d2fc5 ("arm64: dts: qcom: monaco-evk: Add IFP Mezzanine") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-17-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit b35b58535b45441a4521d50215b5668731857c7d) Signed-off-by: Ricardo Salveti --- .../dts/qcom/monaco-evk-ifp-mezzanine.dtso | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso index e6beb4393430..a6e57ec8a1e1 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso @@ -50,15 +50,15 @@ }; &pcie0 { - iommu-map = <0x0 &pcie_smmu 0x0 0x1>, - <0x100 &pcie_smmu 0x1 0x1>, - <0x208 &pcie_smmu 0x2 0x1>, - <0x210 &pcie_smmu 0x3 0x1>, - <0x218 &pcie_smmu 0x4 0x1>, - <0x300 &pcie_smmu 0x5 0x1>, - <0x400 &pcie_smmu 0x6 0x1>, - <0x500 &pcie_smmu 0x7 0x1>, - <0x501 &pcie_smmu 0x8 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0 0x0 0x1>, + <0x100 &pcie_smmu 0x1 0x0 0x1>, + <0x208 &pcie_smmu 0x2 0x0 0x1>, + <0x210 &pcie_smmu 0x3 0x0 0x1>, + <0x218 &pcie_smmu 0x4 0x0 0x1>, + <0x300 &pcie_smmu 0x5 0x0 0x1>, + <0x400 &pcie_smmu 0x6 0x0 0x1>, + <0x500 &pcie_smmu 0x7 0x0 0x1>, + <0x501 &pcie_smmu 0x8 0x0 0x1>; }; &pcieport0 { From 707444b0d6523dcba62acd528fb070f656252711 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 23 Jul 2026 13:48:44 +0200 Subject: [PATCH 06/37] FROMGIT: arm64: dts: monaco: Fix CSI I2C controllers default bus frequency 1 MHz is quite fast for an I2C bus and not necessarly reliable, change this to 400 KHz which is a more reasonable default. Signed-off-by: Hans de Goede Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260723114844.63093-1-johannes.goede@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 1c2935b75f78fa74ef9cc37d95c4f734cbc0c15f) Signed-off-by: Ricardo Salveti --- arch/arm64/boot/dts/qcom/monaco.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 5d34d287fc2e..3241d81a04be 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -5457,14 +5457,14 @@ cci0_i2c0: i2c-bus@0 { reg = <0>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; cci0_i2c1: i2c-bus@1 { reg = <1>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; @@ -5494,14 +5494,14 @@ cci1_i2c0: i2c-bus@0 { reg = <0>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; cci1_i2c1: i2c-bus@1 { reg = <1>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; @@ -5531,14 +5531,14 @@ cci2_i2c0: i2c-bus@0 { reg = <0>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; cci2_i2c1: i2c-bus@1 { reg = <1>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; From 77e253cad68a8e6bc155493242f6d196cee3f72b Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Mon, 9 Feb 2026 19:15:29 +0530 Subject: [PATCH 07/37] UPSTREAM: dt-bindings: pinctrl: qcom,sm8450-lpass-lpi-pinctrl: Add SA8775P and QCS8300 pinctrl Document compatible for Qualcomm SA8775P and QCS8300 SoC LPASS TLMM pin controller, fully compatible with previous SM8450 generation (same amount of pins and functions). Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij (cherry picked from commit 1c5986eefde922cccaa9f74567ddf4cf468d8400) Link: https://lore.kernel.org/r/20260209134529.725573-1-mohammad.rafi.shaik@oss.qualcomm.com [rsalveti: add the Link: trailer, which the upstream commit is missing] Signed-off-by: Ricardo Salveti --- .../bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml index e7565592da86..541c1c54ddb0 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml @@ -15,7 +15,13 @@ description: properties: compatible: - const: qcom,sm8450-lpass-lpi-pinctrl + oneOf: + - const: qcom,sm8450-lpass-lpi-pinctrl + - items: + - enum: + - qcom,qcs8300-lpass-lpi-pinctrl + - qcom,sa8775p-lpass-lpi-pinctrl + - const: qcom,sm8450-lpass-lpi-pinctrl reg: items: From 4936b2c9df464c8424d75f8d8e696af280019d8d Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 13 Mar 2026 10:38:18 +0000 Subject: [PATCH 08/37] UPSTREAM: arm64: dts: qcom: monaco: add dt entry for lpass lpi pinctrl Add LPASS LPI pinctrl node used for setting MI2S and soundwire pin configs. Co-developed-by: Loic Poulain Signed-off-by: Loic Poulain Signed-off-by: Srinivas Kandagatla Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260313103824.2634519-4-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit faf08fd43411d8ebcc30bd96a05ac4aa31aac66b) Signed-off-by: Ricardo Salveti --- arch/arm64/boot/dts/qcom/monaco.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 3241d81a04be..58d1cc3faf1c 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -22,6 +22,7 @@ #include #include #include +#include #include / { @@ -2879,6 +2880,20 @@ }; }; + lpass_tlmm: pinctrl@3440000 { + compatible = "qcom,qcs8300-lpass-lpi-pinctrl", "qcom,sm8450-lpass-lpi-pinctrl"; + reg = <0x0 0x03440000 0x0 0x20000>, + <0x0 0x034d0000 0x0 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + }; + lpass_ag_noc: interconnect@3c40000 { compatible = "qcom,qcs8300-lpass-ag-noc"; reg = <0x0 0x03c40000 0x0 0x17200>; From f7bd5d72b8dc795be19e6435355e4fcf6370cbef Mon Sep 17 00:00:00 2001 From: Riccardo Mereu Date: Thu, 20 Nov 2025 16:58:20 +0100 Subject: [PATCH 09/37] UPSTREAM: dt-bindings: vendor-prefixes: Add Arduino name Add entry for Arduino SRL (https://arduino.cc) Signed-off-by: Riccardo Mereu Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251120155825.121483-2-r.mereu.kernel@arduino.cc Signed-off-by: Bjorn Andersson (cherry picked from commit d16ffac771715a8c94611b6f8088a3e800bcf5bf) Signed-off-by: Ricardo Salveti --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 7fa32190761b..5c46fe72204b 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -154,6 +154,8 @@ patternProperties: description: Arctic Sand "^arcx,.*": description: arcx Inc. / Archronix Inc. + "^arduino,.*": + description: Arduino SRL "^argon40,.*": description: Argon 40 Technologies Limited "^ariaboard,.*": From 452caf707e2e1e1b3ed7a2feb3cb0432007c094d Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Fri, 13 Mar 2026 10:38:20 +0000 Subject: [PATCH 10/37] BACKPORT: dt-bindings: arm: qcom: add Arduino Monza, VENTUNO Q Document Arduino monza, VENTUNO Q codename. It combines Monaco based SoM with STMicroelectronics STM32H5 microcontroller. Signed-off-by: Loic Poulain Co-developed-by: Srinivas Kandagatla Signed-off-by: Srinivas Kandagatla Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260313103824.2634519-6-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit f2915f6721e770ea7a00cf20c6488ac1f95d826f) [rsalveti: keep the downstream qcom,monaco-ac-evk entry alongside it] Signed-off-by: Ricardo Salveti --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f0359455dc20..41da143c74a5 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -867,6 +867,7 @@ properties: - items: - enum: + - arduino,monza - qcom,monaco-ac-evk - qcom,monaco-evk - qcom,qcs8300-ride From 438710cf0db3172fae9c991e74331c9709c980ef Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Fri, 13 Mar 2026 10:38:19 +0000 Subject: [PATCH 11/37] UPSTREAM: arm64: dts: qcom: Add Monaco Monza SoM The Monaco Monza SoM is a compact computing module that integrates a Monaco/QCS8300 System on Chip (SoC), along with essential components optimized for IoT applications. It is designed to be mounted on carrier boards, enabling the development of complete embedded systems. The following components are described: - Fixed S2S 1.8V rail - PMM8654AU RPMh regulators (PMIC A and PMIC C) - Display subsystem/phy supplies (DSI, DP) - Enable GPU, GPI DMA, IRIS - PCIe Gen4 for both controllers and PHY supply hookups - QUPv3 firmware declarations - REFGEN always-on workaround for USB2 HS PHY - Remoteproc firmware names for ADSP, CDSP and GPDSP - Ethernet SERDES supplies - USB HS/SS PHY regulators - On-SoM eMMC Signed-off-by: Loic Poulain Co-developed-by: Srinivas Kandagatla Signed-off-by: Srinivas Kandagatla Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260313103824.2634519-5-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 5238f4e7169fe908379ef991e320b1641c21fcbe) Signed-off-by: Ricardo Salveti --- .../arm64/boot/dts/qcom/monaco-monza-som.dtsi | 323 ++++++++++++++++++ 1 file changed, 323 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi diff --git a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi new file mode 100644 index 000000000000..9b5ed55939b8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +#include "monaco.dtsi" +#include "monaco-pmics.dtsi" + +/ { + /* This comes from a PMIC handled within the SAIL domain */ + vreg_s2s: vreg-s2s { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2s"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + regulator-always-on; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s5c: smps5 { /* LPDDR VDD2H */ + regulator-name = "vreg_s5c"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + }; + + vreg_l1c: ldo1 { /* LPDDR VDDQ */ + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <512000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2c: ldo2 { /* LPDDR VDD2L */ + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8c: ldo8 { /* LPDDR VDD1 */ + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9c: ldo9 { /* QFPROM */ + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +&mdss_dp0 { + pinctrl-0 = <&dp_hpd>; + pinctrl-names = "default"; +}; + +&mdss_dp0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l4a>; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l5a>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l4a>; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs8300/a623_zap.mbn"; +}; + +&iris { + status = "okay"; +}; + +/* PCIe0 Gen4 x2 */ +&pcie0 { + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>, + <0x200 &pcie_smmu 0x0007 0x1>, + <0x208 &pcie_smmu 0x0002 0x1>, + <0x210 &pcie_smmu 0x0003 0x1>, + <0x218 &pcie_smmu 0x0004 0x1>, + <0x300 &pcie_smmu 0x0005 0x1>, + <0x400 &pcie_smmu 0x0006 0x1>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +/* PCIe1 Gen4 x4 */ +&pcie1 { + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&qupv3_id_0 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; + + status = "okay"; +}; + +&qupv3_id_1 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; + status = "okay"; +}; + +/* There is a HW/FW issue preventing proper REFGEN hardware voting + * for the USB2 HS PHY. As a workaround, we force REFGEN to stay + * always‑on in software, matching initial bootloader config. + */ +&refgen { + regulator-always-on; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs8300/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs8300/cdsp0.mbn"; + + status = "okay"; +}; + +&remoteproc_gpdsp { + firmware-name = "qcom/qcs8300/gpdsp0.mbn"; + + status = "okay"; +}; + +/* OnSom eMMC */ +&sdhc_1 { + vmmc-supply = <&vreg_l8a>; + vqmmc-supply = <&vreg_s2s>; + + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + no-sd; + no-sdio; + non-removable; + + status = "okay"; +}; + +/* Ethernet/SGMII */ +&serdes0 { + phy-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&tlmm { + dp_hpd: dp-hpd-state { + pins = "gpio94"; + function = "edp0_hot"; + bias-disable; + }; +}; + +/* USB0 HS + SS */ +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +/* USB1 HS */ +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; From aeb013fe84e3a078774f7a3c9730082c4f977928 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Fri, 13 Mar 2026 10:38:21 +0000 Subject: [PATCH 12/37] BACKPORT: arm64: dts: qcom: Add Arduino Monza (VENTUNO Q) board support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device tree support for the Arduino VENTUNO Q board, based on the Qualcomm QCS8300 (Monaco) SoC. The board features a Qualcomm Monza SoM and integrates various peripherals, including: - USB Type‑C connector with dual‑role support - ADV7535 DSI‑to‑HDMI bridge - MAX98091 audio codec - 2.5G Ethernet PHY (HSGMII) - PCIe0 (to onboard WiFi chipset and USB bridge) - PCIe1 (to M2/nvme) - Button (via GPIO‑keys) Signed-off-by: Loic Poulain Co-developed-by: Srinivas Kandagatla Signed-off-by: Srinivas Kandagatla Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260313103824.2634519-7-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 70e3a6120ef7d3943be4ab291031d0bf10a954ab) [rsalveti: context-only Makefile conflict; mahua-crd and milos-fairphone-fp6 surround the new entry upstream but are not on this branch] Signed-off-by: Ricardo Salveti --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/monaco-arduino-monza.dts | 466 ++++++++++++++++++ arch/arm64/boot/dts/qcom/monaco.dtsi | 55 +++ 3 files changed, 522 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6577a1c826bc..625640cac092 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -62,6 +62,7 @@ lemans-evk-ifp-mezzanine-dtbs := lemans-evk.dtb lemans-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtbo +dtb-$(CONFIG_ARCH_QCOM) += monaco-arduino-monza.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-ac-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts new file mode 100644 index 000000000000..ca14f0ea4dae --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include +#include + +#include "monaco.dtsi" +#include "monaco-pmics.dtsi" +#include "monaco-monza-som.dtsi" + +/ { + model = "Arduino VENTUNO Q"; + compatible = "arduino,monza", "qcom,qcs8300"; + + aliases { + ethernet0 = ðernet0; + i2c1 = &i2c1; + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-home { + label = "Home Key"; + linux,code = ; + gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + + sound { + compatible = "qcom,qcs8275-sndcard"; + model = "arduino-monza"; + audio-routing = "IN12", "Headset Mic12", + "Headset Mic12", "MICBIAS", + "IN56", "Headset Mic56", + "Headset Mic56", "MICBIAS", + "MIC1", "MICBIAS", + "Headphone", "HPL", + "Headphone", "HPR", + "Receiver", "RCVL", + "Receiver", "RCVR", + "Speaker", "SPKL", + "Speaker", "SPKR"; + + pinctrl-0 = <&quad_mi2s_active>, <&quad_mclk_active>, <&lpi_i2s4_active>; + pinctrl-names = "default"; + + pri-i2s-playback-dai-link { + link-name = "Analog Playback"; + + codec { + sound-dai = <&max98091>; + }; + + cpu { + sound-dai = <&q6apmbedai 137>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + pri-i2s-capture-dai-link { + link-name = "Analog Capture"; + + codec { + sound-dai = <&max98091>; + }; + + cpu { + sound-dai = <&q6apmbedai 138>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + hdmi-mi2s-playback-dai-link { + link-name = "HDMI Playback"; + + codec { + sound-dai = <&adv7535>; + }; + + cpu { + sound-dai = <&q6apmbedai 145>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vdc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdc_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vdc_5v: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdc_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + startup-delay-us = <20000>; + }; + + vreg_nvme: regulator-3p3-m2 { + compatible = "regulator-fixed"; + regulator-name = "vreg_m2_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <20000>; + }; +}; + +ðernet0 { + phy-mode = "2500base-x"; + phy-handle = <&hsgmii_phy0>; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + hsgmii_phy0: ethernet-phy@1c { + compatible = "ethernet-phy-id004d.d101"; + reg = <0x1c>; + reset-gpios = <&tlmm 50 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +&i2c12 { + clock-frequency = <400000>; + + status = "okay"; + + max98091: audio-codec@10 { + compatible = "maxim,max98091"; + reg = <0x10>; + pinctrl-0 = <&max98091_default>; + pinctrl-names = "default"; + interrupts-extended = <&tlmm 16 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_16 */ + clocks = <&q6prmcc LPASS_CLK_ID_MCLK_3 LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; + + adv7535: bridge@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + pinctrl-0 = <&adv7535_default>; + pinctrl-names = "default"; + interrupts-extended = <&tlmm 93 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <&vdc_1v8>; + dvdd-supply = <&vdc_1v8>; + pvdd-supply = <&vdc_1v8>; + a2vdd-supply = <&vdc_1v8>; + v3p3-supply = <&vdc_3v3>; + v1p2-supply = <&vdc_1v8>; + adi,dsi-lanes = <4>; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp0_phy { + status = "okay"; +}; + +&mdss_dsi0 { + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&adv7535_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + vddpe-3v3-supply = <&vdc_3v3>; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + vddpe-3v3-supply = <&vreg_nvme>; +}; + +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + + pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x01 0xff>; + ranges; + reg = <0x010000 0x00 0x00 0x00 0x00>; + + pci@2,0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges; + reg = <0x021000 0x00 0x00 0x00 0x00>; + + usb@0 { + compatible = "pci104c,8241"; + reg = <0 0 0 0 0>; + ti,pwron-active-high; + }; + }; + }; +}; + +&pcieport1 { + reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; +}; + +&tlmm { + pcie0_default_state: pcie0-default-state { + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio5"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio6"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + max98091_default: max98091-default-state { + pins = "gpio16"; + function = "gpio"; + bias-pull-up; + }; + + pcie1_default_state: pcie1-default-state { + wake-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio22"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio79"; + function = "gpio"; + bias-disable; + }; + + adv7535_default: adv7535-default-state { + pins = "gpio93"; + function = "gpio"; + bias-pull-up; + }; +}; + +&uart7 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +/* Internally connected to the MCU (e.g. for DFU). */ +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 58d1cc3faf1c..92826c08a858 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2892,6 +2892,61 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 23>; + + quad_mclk_active: quad-mclk-state { + clk-pins { + pins = "gpio5"; + function = "ext_mclk1_c"; + drive-strength = <8>; + bias-disable; + }; + }; + + quad_mi2s_active: quad-active-state { + data-pins { + pins = "gpio2", "gpio3"; + function = "qua_mi2s_data"; + drive-strength = <8>; + bias-disable; + }; + + sclk-pins { + pins = "gpio0"; + function = "qua_mi2s_sclk"; + drive-strength = <8>; + bias-disable; + }; + + ws-pins { + pins = "gpio1"; + function = "qua_mi2s_ws"; + drive-strength = <8>; + bias-disable; + }; + }; + + lpi_i2s4_active: lpi_i2s4-active-state { + data0-pins { + pins = "gpio17"; + function = "i2s4_data"; + drive-strength = <8>; + bias-disable; + }; + + clk-pins { + pins = "gpio12"; + function = "i2s4_clk"; + drive-strength = <8>; + bias-disable; + }; + + ws-pins { + pins = "gpio13"; + function = "i2s4_ws"; + drive-strength = <8>; + bias-disable; + }; + }; }; lpass_ag_noc: interconnect@3c40000 { From 24002476542209e8df5381a71bf2a5937f6605c8 Mon Sep 17 00:00:00 2001 From: Shuai Zhang Date: Wed, 29 Apr 2026 18:35:37 +0800 Subject: [PATCH 13/37] UPSTREAM: arm64: dts: qcom: monaco-arduino-monza: Add Bluetooth UART node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The QCA2066 Bluetooth chip is powered by a board-level 3.3 V supply provided by the hardware. This change connects the Bluetooth controller via UART10, and the corresponding GPIO is used to enable the Bluetooth chip. basic function test step: - bluetoothctl power on/off - bluetoothctl scan bredr/le - bluetoothctl pair - bluetoothctl connect low-state test and state: - rtcwake -d /dev/rtc0 -m no -s 30 && systemctl suspend cat /sys/kernel/debug/suspend_stats success: 1 fail: 0 failed_freeze: 0 failed_prepare: 0 failed_suspend: 0 failed_suspend_late: 0 failed_suspend_noirq: 0 failed_resume: 0 failed_resume_early: 0 failed_resume_noirq: 0 failures: last_failed_dev: last_failed_errno: 0 0 last_failed_step: Signed-off-by: Shuai Zhang Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260429103537.1282497-1-shuai.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 0299c007e6f34a2a5b724c332b86be77409ea729) Signed-off-by: Ricardo Salveti --- arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index ca14f0ea4dae..379b796f261f 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -21,6 +21,7 @@ ethernet0 = ðernet0; i2c1 = &i2c1; serial0 = &uart7; + serial1 = &uart10; }; chosen { @@ -454,6 +455,16 @@ status = "okay"; }; +&uart10 { + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,qca2066-bt"; + enable-gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>; + clocks = <&sleep_clk>; + }; +}; + &usb_1 { status = "okay"; }; From bc29d73a88dbff5e6a5d32f6b5a4ed23d22080ba Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 17 Jun 2026 12:20:26 +0200 Subject: [PATCH 14/37] UPSTREAM: arm64: dts: qcom: monaco-arduino-monza: Remove duplicate includes monaco-arduino-monza.dts includes monaco-monza-som.dtsi, which aleady includes monaco.dtsi and monaco-pmics.dtsi. Remove the duplicates. The resulting DTB file is identical. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260617-topic-monza_includes-v1-1-fcef9ce489fb@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 81a1e944d3b8322468e95549a9c5aed4fc3465d2) Signed-off-by: Ricardo Salveti --- arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index 379b796f261f..f475e2078451 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -9,8 +9,6 @@ #include #include -#include "monaco.dtsi" -#include "monaco-pmics.dtsi" #include "monaco-monza-som.dtsi" / { From 629493679fa786097ed8339ef47aa6d2b301b482 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:57 +0200 Subject: [PATCH 15/37] FROMGIT: arm64: dts: qcom: monaco-monza-som: Fix the PCIe iommu-map entries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 5238f4e7169f ("arm64: dts: qcom: Add Monaco Monza SoM") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-16-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit d7ae79013e6c9b2374948d70856045cc84c9261d) Signed-off-by: Ricardo Salveti --- arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi index 9b5ed55939b8..36af1ad2105d 100644 --- a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi @@ -196,14 +196,14 @@ /* PCIe0 Gen4 x2 */ &pcie0 { - iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>, - <0x200 &pcie_smmu 0x0007 0x1>, - <0x208 &pcie_smmu 0x0002 0x1>, - <0x210 &pcie_smmu 0x0003 0x1>, - <0x218 &pcie_smmu 0x0004 0x1>, - <0x300 &pcie_smmu 0x0005 0x1>, - <0x400 &pcie_smmu 0x0006 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>, + <0x100 &pcie_smmu 0x0001 0x0 0x1>, + <0x200 &pcie_smmu 0x0007 0x0 0x1>, + <0x208 &pcie_smmu 0x0002 0x0 0x1>, + <0x210 &pcie_smmu 0x0003 0x0 0x1>, + <0x218 &pcie_smmu 0x0004 0x0 0x1>, + <0x300 &pcie_smmu 0x0005 0x0 0x1>, + <0x400 &pcie_smmu 0x0006 0x0 0x1>; status = "okay"; }; From f5fb0a97bd07bafeb9687b8f53222d3c3981faaa Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Tue, 21 Apr 2026 12:16:06 +0200 Subject: [PATCH 16/37] FROMGIT: arm64: dts: qcom: monaco-arduino-monza: add USB-C controller and connector Add the Cypress USB Type-C controller and associated connector. The controller is connected over I2C12 and wired to the USB1 DWC3. The USB-C connector routes both high-speed and super-speed signals. Enable dual-role data and power over the USB-C connector. Signed-off-by: Loic Poulain Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260421101606.411335-1-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit f470169a802ede2f3b17a7ede77974c6fe2f5668) Signed-off-by: Ricardo Salveti --- .../boot/dts/qcom/monaco-arduino-monza.dts | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index f475e2078451..c08d50d1c16d 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -244,6 +244,46 @@ status = "okay"; + typec@8 { + compatible = "cypress,cypd4226"; + reg = <0x08>; + pinctrl-0 = <&typec_default_state>; + pinctrl-names = "default"; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ucsi_hs_ccg_p0: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + ucsi_ss_ccg_p0: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + max98091: audio-codec@10 { compatible = "maxim,max98091"; reg = <0x10>; @@ -391,6 +431,12 @@ }; }; + typec_default_state: typec-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { pins = "gpio5"; @@ -467,6 +513,14 @@ status = "okay"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&ucsi_hs_ccg_p0>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&ucsi_ss_ccg_p0>; +}; + /* Internally connected to the MCU (e.g. for DFU). */ &usb_2 { dr_mode = "host"; From 268f557b69dd73ae47d866a8304a60a381626ff6 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Tue, 9 Jun 2026 11:12:06 +0200 Subject: [PATCH 17/37] FROMGIT: arm64: dts: qcom: monaco-arduino-monza: Add fan controller and thermal cooling Enable the CCI1 bus and add support for the Microchip EMC2305 fan controller on the Monaco Arduino Monza board. The controller is virtually implemented by the onboard MCU. Add a new active trip point to the cpuss0 thermal zone and associate it with onboard fan cooling. The CPU subsystem sensor is used as the thermal reference until support for a more appropriate onboard/skin sensor becomes available (via spmi-adc5-gen3). Reviewed-by: Konrad Dybcio Signed-off-by: Loic Poulain Link: https://lore.kernel.org/r/20260609091206.522331-1-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 07d76600a3c59e01430c9a793dc646941be423b9) Signed-off-by: Ricardo Salveti --- .../boot/dts/qcom/monaco-arduino-monza.dts | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index c08d50d1c16d..ddd3e25b97b4 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -7,6 +7,7 @@ #include #include +#include #include #include "monaco-monza-som.dtsi" @@ -154,6 +155,26 @@ }; }; +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + fan_controller: fan-controller@2f { + compatible = "microchip,emc2305"; + reg = <0x2f>; + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <3>; + + fan: fan@0 { + reg = <0x0>; + pwms = <&fan_controller 26000 PWM_POLARITY_INVERTED 1>; + #cooling-cells = <2>; + }; + }; +}; + ðernet0 { phy-mode = "2500base-x"; phy-handle = <&hsgmii_phy0>; @@ -407,6 +428,27 @@ reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; }; +&thermal_zones { + cpuss-0-0-thermal { + polling-delay = <2000>; + + trips { + cpuss0_active: cpuss-active { + temperature = <32000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map-active { + trip = <&cpuss0_active>; + cooling-device = <&fan 0 THERMAL_NO_LIMIT>; + }; + }; + }; +}; + &tlmm { pcie0_default_state: pcie0-default-state { wake-pins { From 704a2d15f099141b5e472fc317dab71cd6c4ae32 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 22 May 2026 10:00:26 +0000 Subject: [PATCH 18/37] FROMGIT: arm64: dts: qcom: Add Display Port audio on Arduino Monza Add support for Display port Audio on Arduino VENTUNO-Q board. Signed-off-by: Srinivas Kandagatla CC: Loic Poulain Reviewed-by: Konrad Dybcio Tested-by: Loic Poulain Link: https://lore.kernel.org/r/20260522100026.94760-1-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit f9665fc0681c1a0edc03be9900ba3f318fe3c5bd) Signed-off-by: Ricardo Salveti --- .../arm64/boot/dts/qcom/monaco-arduino-monza.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index ddd3e25b97b4..7d75a5466950 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -117,6 +117,22 @@ sound-dai = <&q6apm>; }; }; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; }; vdc_3v3: regulator-3v3 { From 3e0d6013f2a5361890e2dd3922cd114b31038a6f Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 11 Jun 2026 16:05:24 +0200 Subject: [PATCH 19/37] BACKPORT: dt-bindings: hwmon: ina2xx: add ina232 compatible The INA232 is a current/power monitor from Texas Instruments sharing the same register map as the other INA2xx. Signed-off-by: Martino Facchin Signed-off-by: Loic Poulain Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260611-monza-ina232-v2-1-e4375ce652d0@oss.qualcomm.com Signed-off-by: Guenter Roeck (cherry picked from commit 6fe4043c161978e6fbcd8eee4f23b119279bf705) [rsalveti: context-only conflict; this branch's compatible lists differ from upstream, the ti,ina232 entries added are unchanged] Signed-off-by: Ricardo Salveti --- Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml index d3cde8936686..bbbd7aae8600 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml @@ -28,6 +28,7 @@ properties: - ti,ina228 - ti,ina230 - ti,ina231 + - ti,ina232 - ti,ina233 - ti,ina237 - ti,ina238 @@ -113,6 +114,7 @@ allOf: - ti,ina228 - ti,ina230 - ti,ina231 + - ti,ina232 - ti,ina237 - ti,ina238 - ti,ina260 @@ -134,6 +136,7 @@ allOf: - ti,ina226 - ti,ina230 - ti,ina231 + - ti,ina232 - ti,ina260 - ti,ina700 - ti,ina780 From ac740fb7bd8c5e0adf55e2d368872f7d6b13dea2 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 11 Jun 2026 16:05:26 +0200 Subject: [PATCH 20/37] FROMGIT: arm64: dts: qcom: monaco-arduino-monza: add ina232 power sensor The Arduino Monza board has a TI INA232 current/power monitor connected on I2C12 at address 0x40. It is used to measure the board supply current through a 2 milliohms shunt resistor. Signed-off-by: Loic Poulain Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260611-monza-ina232-v2-3-e4375ce652d0@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit f2a11bf61bb28f7c1aba4e5c986d56e0e6fade8f) Signed-off-by: Ricardo Salveti --- arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index 7d75a5466950..d1346ca5dd4e 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -366,6 +366,12 @@ }; }; }; + + power-sensor@40 { + compatible = "ti,ina232"; + reg = <0x40>; + shunt-resistor = <2000>; + }; }; &mdss { From ae490f6eb391b5dad64a5a8d95b30e6ad0f91d1f Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Fri, 20 Feb 2026 13:20:21 +0200 Subject: [PATCH 21/37] UPSTREAM: hwmon: (ina2xx) Make it easier to add more devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Make sysfs entries documentation easier to maintain. * Use multi-line enum. * Correct "has_power_average" comment. Create a new "has_update_interval" member for chips which support averaging. Signed-off-by: Ian Ray Reviewed-by: Bence Csókás # v2 Tested-by: Jens Almer Link: https://lore.kernel.org/r/20260220112024.97446-3-ian.ray@gehealthcare.com Signed-off-by: Guenter Roeck (cherry picked from commit f6e14b5bcabf4ee97a2d535c3c2d7e72c8da4c15) Signed-off-by: Ricardo Salveti --- Documentation/hwmon/ina2xx.rst | 12 ++++++++++-- drivers/hwmon/ina2xx.c | 18 ++++++++++++++---- 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/Documentation/hwmon/ina2xx.rst b/Documentation/hwmon/ina2xx.rst index a3860aae444c..a4ddf4bd2b08 100644 --- a/Documentation/hwmon/ina2xx.rst +++ b/Documentation/hwmon/ina2xx.rst @@ -124,8 +124,16 @@ power1_input Power(uW) measurement channel shunt_resistor Shunt resistance(uOhm) channel (not for ina260) ======================= =============================================== -Additional sysfs entries for ina226, ina230, ina231, ina260, and sy24655 ------------------------------------------------------------------------- +Additional sysfs entries +------------------------ + +Additional entries are available for the following chips: + + * ina226 + * ina230 + * ina231 + * ina260 + * sy24655 ======================= ==================================================== curr1_lcrit Critical low current diff --git a/drivers/hwmon/ina2xx.c b/drivers/hwmon/ina2xx.c index bc3c1f7314b3..afd0018a17e0 100644 --- a/drivers/hwmon/ina2xx.c +++ b/drivers/hwmon/ina2xx.c @@ -135,13 +135,19 @@ static const struct regmap_config ina2xx_regmap_config = { .writeable_reg = ina2xx_writeable_reg, }; -enum ina2xx_ids { ina219, ina226, ina260, sy24655 }; +enum ina2xx_ids { + ina219, + ina226, + ina260, + sy24655 +}; struct ina2xx_config { u16 config_default; bool has_alerts; /* chip supports alerts and limits */ bool has_ishunt; /* chip has internal shunt resistor */ - bool has_power_average; /* chip has internal shunt resistor */ + bool has_power_average; /* chip supports average power */ + bool has_update_interval; int calibration_value; int shunt_div; int bus_voltage_shift; @@ -172,6 +178,7 @@ static const struct ina2xx_config ina2xx_config[] = { .has_alerts = false, .has_ishunt = false, .has_power_average = false, + .has_update_interval = false, }, [ina226] = { .config_default = INA226_CONFIG_DEFAULT, @@ -183,6 +190,7 @@ static const struct ina2xx_config ina2xx_config[] = { .has_alerts = true, .has_ishunt = false, .has_power_average = false, + .has_update_interval = true, }, [ina260] = { .config_default = INA260_CONFIG_DEFAULT, @@ -193,6 +201,7 @@ static const struct ina2xx_config ina2xx_config[] = { .has_alerts = true, .has_ishunt = true, .has_power_average = false, + .has_update_interval = true, }, [sy24655] = { .config_default = SY24655_CONFIG_DEFAULT, @@ -204,6 +213,7 @@ static const struct ina2xx_config ina2xx_config[] = { .has_alerts = true, .has_ishunt = false, .has_power_average = true, + .has_update_interval = false, }, }; @@ -713,7 +723,7 @@ static umode_t ina2xx_is_visible(const void *_data, enum hwmon_sensor_types type const struct ina2xx_data *data = _data; bool has_alerts = data->config->has_alerts; bool has_power_average = data->config->has_power_average; - enum ina2xx_ids chip = data->chip; + bool has_update_interval = data->config->has_update_interval; switch (type) { case hwmon_in: @@ -775,7 +785,7 @@ static umode_t ina2xx_is_visible(const void *_data, enum hwmon_sensor_types type case hwmon_chip: switch (attr) { case hwmon_chip_update_interval: - if (chip == ina226 || chip == ina260) + if (has_update_interval) return 0644; break; default: From c7c9139f8b294d3c90cc82d378ab7346ed9fca92 Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Fri, 20 Feb 2026 13:20:20 +0200 Subject: [PATCH 22/37] BACKPORT: dt-bindings: hwmon: ti,ina2xx: Add INA234 device Add a compatible string for the INA234 device, which is like INA226 but has different scaling. Note that the device tree compatible must be different since the driver uses the compatible to configure the scaling. Signed-off-by: Ian Ray Reviewed-by: Krzysztof Kozlowski # v1 Tested-by: Jens Almer Link: https://lore.kernel.org/r/20260220112024.97446-2-ian.ray@gehealthcare.com Signed-off-by: Guenter Roeck (cherry picked from commit ddc3dea2e4248c6f4692c0e70fe96f9ff76aad0e) [rsalveti: context-only conflict; ti,ina232 was added to the same enums earlier in this series] Signed-off-by: Ricardo Salveti --- Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml index bbbd7aae8600..a79ade3142fa 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml @@ -30,6 +30,7 @@ properties: - ti,ina231 - ti,ina232 - ti,ina233 + - ti,ina234 - ti,ina237 - ti,ina238 - ti,ina260 @@ -115,6 +116,7 @@ allOf: - ti,ina230 - ti,ina231 - ti,ina232 + - ti,ina234 - ti,ina237 - ti,ina238 - ti,ina260 @@ -137,6 +139,7 @@ allOf: - ti,ina230 - ti,ina231 - ti,ina232 + - ti,ina234 - ti,ina260 - ti,ina700 - ti,ina780 From ae32b428ea95578459b1aea4605a5eb4fb7dc962 Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Fri, 20 Feb 2026 13:20:22 +0200 Subject: [PATCH 23/37] UPSTREAM: hwmon: (ina2xx) Add support for INA234 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit INA234 is register compatible to INA226 (excepting manufacturer and die or device id registers) but has different scaling. Signed-off-by: Ian Ray Reviewed-by: Bence Csókás # v2 Tested-by: Jens Almer Tested-by: Jonas Rebmann Link: https://lore.kernel.org/r/20260220112024.97446-4-ian.ray@gehealthcare.com Signed-off-by: Guenter Roeck (cherry picked from commit 88a928eebccdc5445d874ddcbf1683b76c9f1431) Signed-off-by: Ricardo Salveti --- Documentation/hwmon/ina2xx.rst | 13 ++++++++++++- drivers/hwmon/Kconfig | 2 +- drivers/hwmon/ina2xx.c | 18 ++++++++++++++++++ 3 files changed, 31 insertions(+), 2 deletions(-) diff --git a/Documentation/hwmon/ina2xx.rst b/Documentation/hwmon/ina2xx.rst index a4ddf4bd2b08..d64e7af46a12 100644 --- a/Documentation/hwmon/ina2xx.rst +++ b/Documentation/hwmon/ina2xx.rst @@ -74,6 +74,16 @@ Supported chips: https://us1.silergy.com/ + * Texas Instruments INA234 + + Prefix: 'ina234' + + Addresses: I2C 0x40 - 0x43 + + Datasheet: Publicly available at the Texas Instruments website + + https://www.ti.com/ + Author: Lothar Felten Description @@ -89,7 +99,7 @@ interface. The INA220 monitors both shunt drop and supply voltage. The INA226 is a current shunt and power monitor with an I2C interface. The INA226 monitors both a shunt voltage drop and bus supply voltage. -INA230 and INA231 are high or low side current shunt and power monitors +INA230, INA231, and INA234 are high or low side current shunt and power monitors with an I2C interface. The chips monitor both a shunt voltage drop and bus supply voltage. @@ -132,6 +142,7 @@ Additional entries are available for the following chips: * ina226 * ina230 * ina231 + * ina234 * ina260 * sy24655 diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index fdb3ecc2bb04..a4d9b213dcf6 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -2281,7 +2281,7 @@ config SENSORS_INA2XX select REGMAP_I2C help If you say yes here you get support for INA219, INA220, INA226, - INA230, INA231, INA260, and SY24655 power monitor chips. + INA230, INA231, INA234, INA260, and SY24655 power monitor chips. The INA2xx driver is configured for the default configuration of the part as described in the datasheet. diff --git a/drivers/hwmon/ina2xx.c b/drivers/hwmon/ina2xx.c index afd0018a17e0..e07f24901bfb 100644 --- a/drivers/hwmon/ina2xx.c +++ b/drivers/hwmon/ina2xx.c @@ -138,6 +138,7 @@ static const struct regmap_config ina2xx_regmap_config = { enum ina2xx_ids { ina219, ina226, + ina234, ina260, sy24655 }; @@ -192,6 +193,18 @@ static const struct ina2xx_config ina2xx_config[] = { .has_power_average = false, .has_update_interval = true, }, + [ina234] = { + .config_default = INA226_CONFIG_DEFAULT, + .calibration_value = 2048, + .shunt_div = 400, /* 2.5 µV/LSB raw ADC reading from INA2XX_SHUNT_VOLTAGE */ + .bus_voltage_shift = 4, + .bus_voltage_lsb = 25600, + .power_lsb_factor = 32, + .has_alerts = true, + .has_ishunt = false, + .has_power_average = false, + .has_update_interval = true, + }, [ina260] = { .config_default = INA260_CONFIG_DEFAULT, .shunt_div = 400, @@ -1000,6 +1013,7 @@ static const struct i2c_device_id ina2xx_id[] = { { "ina226", ina226 }, { "ina230", ina226 }, { "ina231", ina226 }, + { "ina234", ina234 }, { "ina260", ina260 }, { "sy24655", sy24655 }, { } @@ -1031,6 +1045,10 @@ static const struct of_device_id __maybe_unused ina2xx_of_match[] = { .compatible = "ti,ina231", .data = (void *)ina226 }, + { + .compatible = "ti,ina234", + .data = (void *)ina234 + }, { .compatible = "ti,ina260", .data = (void *)ina260 From 7aa0dcc1fe73eba2691bc81cc98f1c57b11544cd Mon Sep 17 00:00:00 2001 From: Jonas Rebmann Date: Tue, 3 Mar 2026 12:07:02 +0100 Subject: [PATCH 24/37] UPSTREAM: hwmon: (ina2xx) Shift INA234 shunt and current registers The INA219 has the lowest three bits of the bus voltage register zero-reserved, the bus_voltage_shift ina2xx_config field was introduced to accommodate for that. The INA234 has four bits of the bus voltage, of the shunt voltage, and of the current registers zero-reserved but the latter two were implemented by choosing a 16x higher shunt_div instead of a separate field specifying a bit shift. This is possible because shunt voltage and current are divided by shunt_div, hence a 16x higher shunt_div results in a 16x smaller LSB for both the shunt voltage and the current register, perfectly accounting for the missing bit shift. For consistency and correctness, account for the reserved bits via shunt_voltage_shift and current_shift configuration fields as already done for voltage registers and use the conversion constants given in the INA234 datasheet. Signed-off-by: Jonas Rebmann Link: https://lore.kernel.org/r/20260303-ina234-shift-v1-2-318c33ac4480@pengutronix.de Signed-off-by: Guenter Roeck (cherry picked from commit eeca1114d1e2cc0eacaebb80f3f2afbaebfc60be) Signed-off-by: Ricardo Salveti --- drivers/hwmon/ina2xx.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/ina2xx.c b/drivers/hwmon/ina2xx.c index e07f24901bfb..a46a11840672 100644 --- a/drivers/hwmon/ina2xx.c +++ b/drivers/hwmon/ina2xx.c @@ -151,9 +151,11 @@ struct ina2xx_config { bool has_update_interval; int calibration_value; int shunt_div; + int shunt_voltage_shift; int bus_voltage_shift; int bus_voltage_lsb; /* uV */ int power_lsb_factor; + int current_shift; }; struct ina2xx_data { @@ -173,59 +175,69 @@ static const struct ina2xx_config ina2xx_config[] = { .config_default = INA219_CONFIG_DEFAULT, .calibration_value = 4096, .shunt_div = 100, + .shunt_voltage_shift = 0, .bus_voltage_shift = 3, .bus_voltage_lsb = 4000, .power_lsb_factor = 20, .has_alerts = false, .has_ishunt = false, .has_power_average = false, + .current_shift = 0, .has_update_interval = false, }, [ina226] = { .config_default = INA226_CONFIG_DEFAULT, .calibration_value = 2048, .shunt_div = 400, + .shunt_voltage_shift = 0, .bus_voltage_shift = 0, .bus_voltage_lsb = 1250, .power_lsb_factor = 25, .has_alerts = true, .has_ishunt = false, .has_power_average = false, + .current_shift = 0, .has_update_interval = true, }, [ina234] = { .config_default = INA226_CONFIG_DEFAULT, .calibration_value = 2048, - .shunt_div = 400, /* 2.5 µV/LSB raw ADC reading from INA2XX_SHUNT_VOLTAGE */ + .shunt_div = 25, /* 2.5 µV/LSB raw ADC reading from INA2XX_SHUNT_VOLTAGE */ + .shunt_voltage_shift = 4, .bus_voltage_shift = 4, .bus_voltage_lsb = 25600, .power_lsb_factor = 32, .has_alerts = true, .has_ishunt = false, .has_power_average = false, + .current_shift = 4, .has_update_interval = true, }, [ina260] = { .config_default = INA260_CONFIG_DEFAULT, .shunt_div = 400, + .shunt_voltage_shift = 0, .bus_voltage_shift = 0, .bus_voltage_lsb = 1250, .power_lsb_factor = 8, .has_alerts = true, .has_ishunt = true, .has_power_average = false, + .current_shift = 0, .has_update_interval = true, }, [sy24655] = { .config_default = SY24655_CONFIG_DEFAULT, .calibration_value = 4096, .shunt_div = 400, + .shunt_voltage_shift = 0, .bus_voltage_shift = 0, .bus_voltage_lsb = 1250, .power_lsb_factor = 25, .has_alerts = true, .has_ishunt = false, .has_power_average = true, + .current_shift = 0, .has_update_interval = false, }, }; @@ -279,7 +291,8 @@ static int ina2xx_get_value(struct ina2xx_data *data, u8 reg, switch (reg) { case INA2XX_SHUNT_VOLTAGE: /* signed register */ - val = DIV_ROUND_CLOSEST((s16)regval, data->config->shunt_div); + val = (s16)regval >> data->config->shunt_voltage_shift; + val = DIV_ROUND_CLOSEST(val, data->config->shunt_div); break; case INA2XX_BUS_VOLTAGE: val = (regval >> data->config->bus_voltage_shift) * @@ -291,7 +304,8 @@ static int ina2xx_get_value(struct ina2xx_data *data, u8 reg, break; case INA2XX_CURRENT: /* signed register, result in mA */ - val = (s16)regval * data->current_lsb_uA; + val = ((s16)regval >> data->config->current_shift) * + data->current_lsb_uA; val = DIV_ROUND_CLOSEST(val, 1000); break; case INA2XX_CALIBRATION: @@ -385,6 +399,7 @@ static u16 ina226_alert_to_reg(struct ina2xx_data *data, int reg, long val) case INA2XX_SHUNT_VOLTAGE: val = clamp_val(val, 0, SHRT_MAX * data->config->shunt_div); val *= data->config->shunt_div; + val <<= data->config->shunt_voltage_shift; return clamp_val(val, 0, SHRT_MAX); case INA2XX_BUS_VOLTAGE: val = clamp_val(val, 0, 200000); @@ -399,6 +414,7 @@ static u16 ina226_alert_to_reg(struct ina2xx_data *data, int reg, long val) val = clamp_val(val, INT_MIN / 1000, INT_MAX / 1000); /* signed register, result in mA */ val = DIV_ROUND_CLOSEST(val * 1000, data->current_lsb_uA); + val <<= data->config->current_shift; return clamp_val(val, SHRT_MIN, SHRT_MAX); default: /* programmer goofed */ From 809699b75d37b35e07c8d3d7e12cef2fc3418458 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 11 Jun 2026 16:05:25 +0200 Subject: [PATCH 25/37] BACKPORT: hwmon: (ina2xx) Add support for INA232 The INA232 is a current/power monitor. It shares the same register layout as the other chips in the series and uses the INA226 default configuration, but differs in its electrical characteristics: Signed-off-by: Martino Facchin Signed-off-by: Loic Poulain Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260611-monza-ina232-v2-2-e4375ce652d0@oss.qualcomm.com [groeck: Rephrased commit message] Signed-off-by: Guenter Roeck (cherry picked from commit d1db9b08fbf399ace18cb99adfd609d7e5582b73) [rsalveti: keep the positional i2c_device_id initialisers this branch uses; the conversion to designated initialisers is not part of this series] Signed-off-by: Ricardo Salveti --- drivers/hwmon/ina2xx.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/hwmon/ina2xx.c b/drivers/hwmon/ina2xx.c index a46a11840672..74bc85344d3a 100644 --- a/drivers/hwmon/ina2xx.c +++ b/drivers/hwmon/ina2xx.c @@ -138,6 +138,7 @@ static const struct regmap_config ina2xx_regmap_config = { enum ina2xx_ids { ina219, ina226, + ina232, ina234, ina260, sy24655 @@ -213,6 +214,20 @@ static const struct ina2xx_config ina2xx_config[] = { .current_shift = 4, .has_update_interval = true, }, + [ina232] = { + .config_default = INA226_CONFIG_DEFAULT, + .calibration_value = 2048, + .shunt_div = 400, + .shunt_voltage_shift = 0, + .bus_voltage_shift = 0, + .bus_voltage_lsb = 1600, + .power_lsb_factor = 32, + .has_alerts = true, + .has_ishunt = false, + .has_power_average = false, + .current_shift = 0, + .has_update_interval = true, + }, [ina260] = { .config_default = INA260_CONFIG_DEFAULT, .shunt_div = 400, @@ -1029,6 +1044,7 @@ static const struct i2c_device_id ina2xx_id[] = { { "ina226", ina226 }, { "ina230", ina226 }, { "ina231", ina226 }, + { "ina232", ina232 }, { "ina234", ina234 }, { "ina260", ina260 }, { "sy24655", sy24655 }, @@ -1061,6 +1077,10 @@ static const struct of_device_id __maybe_unused ina2xx_of_match[] = { .compatible = "ti,ina231", .data = (void *)ina226 }, + { + .compatible = "ti,ina232", + .data = (void *)ina232 + }, { .compatible = "ti,ina234", .data = (void *)ina234 From 3ac090d4a44a0f72f5a423fb0074bcf3dc8f520b Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 2 Apr 2026 08:11:11 +0000 Subject: [PATCH 26/37] UPSTREAM: ASoC: dt-bindings: qcom: add LPASS LPI MI2S dai ids Add new dai ids entries for LPASS LPI MI2S and SENARY MI2S audio lines. Co-developed-by: Mohammad Rafi Shaik Signed-off-by: Mohammad Rafi Shaik Signed-off-by: Srinivas Kandagatla Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260402081118.348071-7-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Mark Brown (cherry picked from commit e46957f27c6004f3ab5ec456f4e848950364ebc1) Signed-off-by: Ricardo Salveti --- .../bindings/sound/qcom,q6dsp-lpass-ports.yaml | 5 ++++- include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h | 12 ++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml index 08c618e7e428..2b27d6c8f58f 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml @@ -126,13 +126,16 @@ patternProperties: reg: contains: # MI2S DAI ID range PRIMARY_MI2S_RX - QUATERNARY_MI2S_TX and - # QUINARY_MI2S_RX - QUINARY_MI2S_TX + # QUINARY_MI2S_RX - QUINARY_MI2S_TX and + # LPI_MI2S_RX_0 - SENARY_MI2S_TX items: oneOf: - minimum: 16 maximum: 23 - minimum: 127 maximum: 128 + - minimum: 137 + maximum: 148 then: required: - qcom,sd-lines diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h index 41bc1559cf18..bc860fcbf0f5 100644 --- a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h @@ -140,6 +140,18 @@ #define DISPLAY_PORT_RX_6 134 #define DISPLAY_PORT_RX_7 135 #define USB_RX 136 +#define LPI_MI2S_RX_0 137 +#define LPI_MI2S_TX_0 138 +#define LPI_MI2S_RX_1 139 +#define LPI_MI2S_TX_1 140 +#define LPI_MI2S_RX_2 141 +#define LPI_MI2S_TX_2 142 +#define LPI_MI2S_RX_3 143 +#define LPI_MI2S_TX_3 144 +#define LPI_MI2S_RX_4 145 +#define LPI_MI2S_TX_4 146 +#define SENARY_MI2S_RX 147 +#define SENARY_MI2S_TX 148 #define LPASS_CLK_ID_PRI_MI2S_IBIT 1 #define LPASS_CLK_ID_PRI_MI2S_EBIT 2 From 29466cbfa1da3b21ab5e6daa8485fc77ab61c6e8 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 2 Apr 2026 08:11:12 +0000 Subject: [PATCH 27/37] BACKPORT: ASoC: qcom: common: validate cpu dai id during parsing lpass ports numbers have been added but the afe/apm driver never got updated with new max port value that it uses to store dai specific data. There are more than one places these values are cached and always become out of sync. This will result in array out of bounds and weird driver behaviour. To catch such issues, first add a single place where we can define max port and second add a check in common parsing code which can error out before corrupting the memory with out of bounds array access. This should help both avoid and catch these type of mistakes in future. Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20260402081118.348071-8-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Mark Brown (cherry picked from commit d49ee8faefecd4d2eb5c6c9f419f4db9488d68aa) [rsalveti: keep the local qcom_snd_tdm_slot_cfg definition in common.h] Signed-off-by: Ricardo Salveti --- sound/soc/qcom/common.c | 6 ++++++ sound/soc/qcom/common.h | 3 +++ sound/soc/qcom/lpass.h | 3 ++- sound/soc/qcom/qdsp6/q6afe.h | 3 ++- sound/soc/qcom/qdsp6/q6apm.h | 3 ++- 5 files changed, 15 insertions(+), 3 deletions(-) diff --git a/sound/soc/qcom/common.c b/sound/soc/qcom/common.c index df5c7048fcc3..fced8eb951c2 100644 --- a/sound/soc/qcom/common.c +++ b/sound/soc/qcom/common.c @@ -319,6 +319,12 @@ int qcom_snd_parse_of(struct snd_soc_card *card) link->id = args.args[0]; + if (link->id >= LPASS_MAX_PORT) { + dev_err(dev, "%s: Invalid cpu dai id %d\n", link->name, link->id); + ret = -EINVAL; + goto err; + } + if (platform) { link->platforms->of_node = of_parse_phandle(platform, "sound-dai", diff --git a/sound/soc/qcom/common.h b/sound/soc/qcom/common.h index b7d6f617660e..49d901686af7 100644 --- a/sound/soc/qcom/common.h +++ b/sound/soc/qcom/common.h @@ -4,8 +4,11 @@ #ifndef __QCOM_SND_COMMON_H__ #define __QCOM_SND_COMMON_H__ +#include #include +#define LPASS_MAX_PORT (SENARY_MI2S_TX + 1) + struct qcom_snd_tdm_slot_cfg { unsigned int tx_mask; unsigned int rx_mask; diff --git a/sound/soc/qcom/lpass.h b/sound/soc/qcom/lpass.h index de3ec6f594c1..68b71039b981 100644 --- a/sound/soc/qcom/lpass.h +++ b/sound/soc/qcom/lpass.h @@ -14,10 +14,11 @@ #include #include #include +#include "common.h" #include "lpass-hdmi.h" #define LPASS_AHBIX_CLOCK_FREQUENCY 131072000 -#define LPASS_MAX_PORTS (DISPLAY_PORT_RX_7 + 1) +#define LPASS_MAX_PORTS (LPASS_MAX_PORT) #define LPASS_MAX_MI2S_PORTS (8) #define LPASS_MAX_DMA_CHANNELS (8) #define LPASS_MAX_HDMI_DMA_CHANNELS (4) diff --git a/sound/soc/qcom/qdsp6/q6afe.h b/sound/soc/qcom/qdsp6/q6afe.h index a29abe4ce436..0b8c3ec1315c 100644 --- a/sound/soc/qcom/qdsp6/q6afe.h +++ b/sound/soc/qcom/qdsp6/q6afe.h @@ -2,8 +2,9 @@ #ifndef __Q6AFE_H__ #define __Q6AFE_H__ +#include "../common.h" -#define AFE_PORT_MAX 137 +#define AFE_PORT_MAX (LPASS_MAX_PORT) #define MSM_AFE_PORT_TYPE_RX 0 #define MSM_AFE_PORT_TYPE_TX 1 diff --git a/sound/soc/qcom/qdsp6/q6apm.h b/sound/soc/qcom/qdsp6/q6apm.h index bfb6167eba78..f46b5e9a003a 100644 --- a/sound/soc/qcom/qdsp6/q6apm.h +++ b/sound/soc/qcom/qdsp6/q6apm.h @@ -14,9 +14,10 @@ #include #include #include +#include "../common.h" #include "audioreach.h" -#define APM_PORT_MAX 127 +#define APM_PORT_MAX LPASS_MAX_PORT #define APM_PORT_MAX_AUDIO_CHAN_CNT 8 #define PCM_CHANNEL_NULL 0 #define PCM_CHANNEL_FL 1 /* Front left channel. */ From 839681d1257e86ad6e5363a542c0a98cd89088a5 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 2 Apr 2026 08:11:13 +0000 Subject: [PATCH 28/37] UPSTREAM: ASoC: qcom: qdsp6: lpass-ports: add support for LPASS LPI MI2S dais Add support for LPASS LPI MI2S dais in the dai-driver, these dais are used in Monaco based platform devices. Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20260402081118.348071-9-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Mark Brown (cherry picked from commit bcd0df1ebc9d71e2d53e47fd41ff1482753649b0) Signed-off-by: Ricardo Salveti --- sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c | 47 ++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c index 8542e620ee02..d573f2492e27 100644 --- a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c +++ b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c @@ -88,6 +88,42 @@ .id = did, \ } +#define Q6AFE_MI2S_RX_DAI(pre, did) { \ + .playback = { \ + .stream_name = pre" MI2S Playback", \ + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_176400, \ + .formats = SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE, \ + .channels_min = 1, \ + .channels_max = 8, \ + .rate_min = 8000, \ + .rate_max = 176400, \ + }, \ + .name = #did, \ + .id = did, \ + } + +#define Q6AFE_MI2S_TX_DAI(pre, did) { \ + .capture = { \ + .stream_name = pre" MI2S Capture", \ + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_176400, \ + .formats = SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE, \ + .channels_min = 1, \ + .channels_max = 8, \ + .rate_min = 8000, \ + .rate_max = 176400, \ + }, \ + .name = #did, \ + .id = did, \ + } + static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { { .playback = { @@ -480,6 +516,16 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { .id = QUINARY_MI2S_TX, .name = "QUIN_MI2S_TX", }, + Q6AFE_MI2S_RX_DAI("LPI RX0", LPI_MI2S_RX_0), + Q6AFE_MI2S_RX_DAI("LPI RX1", LPI_MI2S_RX_1), + Q6AFE_MI2S_RX_DAI("LPI RX2", LPI_MI2S_RX_2), + Q6AFE_MI2S_RX_DAI("LPI RX3", LPI_MI2S_RX_3), + Q6AFE_MI2S_RX_DAI("LPI RX4", LPI_MI2S_RX_4), + Q6AFE_MI2S_TX_DAI("LPI TX0", LPI_MI2S_TX_0), + Q6AFE_MI2S_TX_DAI("LPI TX1", LPI_MI2S_TX_1), + Q6AFE_MI2S_TX_DAI("LPI TX2", LPI_MI2S_TX_2), + Q6AFE_MI2S_TX_DAI("LPI TX3", LPI_MI2S_TX_3), + Q6AFE_MI2S_TX_DAI("LPI TX4", LPI_MI2S_TX_4), Q6AFE_TDM_PB_DAI("Primary", 0, PRIMARY_TDM_RX_0), Q6AFE_TDM_PB_DAI("Primary", 1, PRIMARY_TDM_RX_1), Q6AFE_TDM_PB_DAI("Primary", 2, PRIMARY_TDM_RX_2), @@ -632,6 +678,7 @@ struct snd_soc_dai_driver *q6dsp_audio_ports_set_config(struct device *dev, break; case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: + case LPI_MI2S_RX_0 ... LPI_MI2S_TX_4: q6dsp_audio_fe_dais[i].ops = cfg->q6i2s_ops; break; case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7: From b9ac5dd53b88cae0b629a4f06c28bfaea885110c Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Thu, 30 Jul 2026 13:43:40 -0400 Subject: [PATCH 29/37] FROMGIT: ASoC: dt-bindings: qcom: q6dsp: add support for lpi mi2s ports 5-6 There are 7 internal MI2S ports per direction found on devices with the internal sound card for Snapdragon 660. This is similar to the LPI MI2S ports, and the LPI MI2S bindings can be reused for internal MI2S. Extend the bindings for LPI MI2S ports to accommodate the internal MI2S ports. Signed-off-by: Richard Acayan Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260730174353.108023-3-mailingradian@gmail.com Signed-off-by: Mark Brown (cherry picked from commit 96591d7030a68ecdbb1be793d4b067d2087e0290) Signed-off-by: Ricardo Salveti --- .../devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml | 4 ++-- include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h | 4 ++++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml index 2b27d6c8f58f..3b03e2acd67e 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml @@ -127,7 +127,7 @@ patternProperties: contains: # MI2S DAI ID range PRIMARY_MI2S_RX - QUATERNARY_MI2S_TX and # QUINARY_MI2S_RX - QUINARY_MI2S_TX and - # LPI_MI2S_RX_0 - SENARY_MI2S_TX + # LPI_MI2S_RX_0 - LPI_MI2S_TX_6 items: oneOf: - minimum: 16 @@ -135,7 +135,7 @@ patternProperties: - minimum: 127 maximum: 128 - minimum: 137 - maximum: 148 + maximum: 152 then: required: - qcom,sd-lines diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h index bc860fcbf0f5..c79d6dc37a5e 100644 --- a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h @@ -152,6 +152,10 @@ #define LPI_MI2S_TX_4 146 #define SENARY_MI2S_RX 147 #define SENARY_MI2S_TX 148 +#define LPI_MI2S_RX_5 149 +#define LPI_MI2S_TX_5 150 +#define LPI_MI2S_RX_6 151 +#define LPI_MI2S_TX_6 152 #define LPASS_CLK_ID_PRI_MI2S_IBIT 1 #define LPASS_CLK_ID_PRI_MI2S_EBIT 2 From a623c07916040372d899f6899f491e4c61ca3290 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Thu, 30 Jul 2026 13:43:44 -0400 Subject: [PATCH 30/37] FROMGIT: ASoC: qdsp6: q6dsp-lpass-ports: add support for lpi mi2s ports 5-6 Add the extra LPI MI2S ports used for internal MI2S on SDM660. Link: https://android.googlesource.com/kernel/msm-extra/+/530cffa4cc977a348753831b163eb9d3302b954a/asoc/msm-dai-q6-v2.c#4597 Signed-off-by: Richard Acayan Reviewed-by: Srinivas Kandagatla Link: https://patch.msgid.link/20260730174353.108023-7-mailingradian@gmail.com Signed-off-by: Mark Brown (cherry picked from commit 68400191e005f44c432c1b18eeca7f5527323a9f) Signed-off-by: Ricardo Salveti --- sound/soc/qcom/common.h | 2 +- sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/sound/soc/qcom/common.h b/sound/soc/qcom/common.h index 49d901686af7..f8cc3079b891 100644 --- a/sound/soc/qcom/common.h +++ b/sound/soc/qcom/common.h @@ -7,7 +7,7 @@ #include #include -#define LPASS_MAX_PORT (SENARY_MI2S_TX + 1) +#define LPASS_MAX_PORT (LPI_MI2S_TX_6 + 1) struct qcom_snd_tdm_slot_cfg { unsigned int tx_mask; diff --git a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c index d573f2492e27..cc247a0813a2 100644 --- a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c +++ b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c @@ -521,11 +521,15 @@ static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { Q6AFE_MI2S_RX_DAI("LPI RX2", LPI_MI2S_RX_2), Q6AFE_MI2S_RX_DAI("LPI RX3", LPI_MI2S_RX_3), Q6AFE_MI2S_RX_DAI("LPI RX4", LPI_MI2S_RX_4), + Q6AFE_MI2S_RX_DAI("LPI RX5", LPI_MI2S_RX_5), + Q6AFE_MI2S_RX_DAI("LPI RX6", LPI_MI2S_RX_6), Q6AFE_MI2S_TX_DAI("LPI TX0", LPI_MI2S_TX_0), Q6AFE_MI2S_TX_DAI("LPI TX1", LPI_MI2S_TX_1), Q6AFE_MI2S_TX_DAI("LPI TX2", LPI_MI2S_TX_2), Q6AFE_MI2S_TX_DAI("LPI TX3", LPI_MI2S_TX_3), Q6AFE_MI2S_TX_DAI("LPI TX4", LPI_MI2S_TX_4), + Q6AFE_MI2S_TX_DAI("LPI TX5", LPI_MI2S_TX_5), + Q6AFE_MI2S_TX_DAI("LPI TX6", LPI_MI2S_TX_6), Q6AFE_TDM_PB_DAI("Primary", 0, PRIMARY_TDM_RX_0), Q6AFE_TDM_PB_DAI("Primary", 1, PRIMARY_TDM_RX_1), Q6AFE_TDM_PB_DAI("Primary", 2, PRIMARY_TDM_RX_2), @@ -679,6 +683,7 @@ struct snd_soc_dai_driver *q6dsp_audio_ports_set_config(struct device *dev, case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: case LPI_MI2S_RX_0 ... LPI_MI2S_TX_4: + case LPI_MI2S_RX_5 ... LPI_MI2S_TX_6: q6dsp_audio_fe_dais[i].ops = cfg->q6i2s_ops; break; case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7: From 4220f531b05b07499a593be36cd3799f35586efb Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Thu, 30 Jul 2026 13:43:45 -0400 Subject: [PATCH 31/37] BACKPORT: ASoC: qdsp6: q6afe: add internal mi2s support The bindings for LPI MI2S ports, originally exclusive to q6apm, can be used for internal MI2S ports on q6afe. Add the port mappings for internal MI2S, found on the Snapdragon 660 internal sound card. Signed-off-by: Richard Acayan Reviewed-by: Srinivas Kandagatla Link: https://patch.msgid.link/20260730174353.108023-8-mailingradian@gmail.com Signed-off-by: Mark Brown (cherry picked from commit bfe9098dc275a319c6b9f6e2417bb60fb8738a4b) [rsalveti: context-only conflicts around the AFE port id defines and the port switch; the added lines themselves are unchanged] Signed-off-by: Ricardo Salveti --- sound/soc/qcom/qdsp6/q6afe.c | 56 ++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/sound/soc/qcom/qdsp6/q6afe.c b/sound/soc/qcom/qdsp6/q6afe.c index 7b59d514b432..98fc8c33b30e 100644 --- a/sound/soc/qcom/qdsp6/q6afe.c +++ b/sound/soc/qcom/qdsp6/q6afe.c @@ -130,6 +130,20 @@ #define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007 #define AFE_PORT_ID_QUINARY_MI2S_RX 0x1016 #define AFE_PORT_ID_QUINARY_MI2S_TX 0x1017 +#define AFE_PORT_ID_INT0_MI2S_RX 0x102e +#define AFE_PORT_ID_INT0_MI2S_TX 0x102f +#define AFE_PORT_ID_INT1_MI2S_RX 0x1030 +#define AFE_PORT_ID_INT1_MI2S_TX 0x1031 +#define AFE_PORT_ID_INT2_MI2S_RX 0x1032 +#define AFE_PORT_ID_INT2_MI2S_TX 0x1033 +#define AFE_PORT_ID_INT3_MI2S_RX 0x1034 +#define AFE_PORT_ID_INT3_MI2S_TX 0x1035 +#define AFE_PORT_ID_INT4_MI2S_RX 0x1036 +#define AFE_PORT_ID_INT4_MI2S_TX 0x1037 +#define AFE_PORT_ID_INT5_MI2S_RX 0x1038 +#define AFE_PORT_ID_INT5_MI2S_TX 0x1039 +#define AFE_PORT_ID_INT6_MI2S_RX 0x103a +#define AFE_PORT_ID_INT6_MI2S_TX 0x103b /* Start of the range of port IDs for TDM devices. */ #define AFE_PORT_ID_TDM_PORT_RANGE_START 0x9000 @@ -925,6 +939,34 @@ static struct afe_port_map port_maps[AFE_PORT_MAX] = { [RX_CODEC_DMA_RX_7] = { AFE_PORT_ID_RX_CODEC_DMA_RX_7, RX_CODEC_DMA_RX_7, 1, 1}, [USB_RX] = { AFE_PORT_ID_USB_RX, USB_RX, 1, 1}, + [LPI_MI2S_RX_0] = { AFE_PORT_ID_INT0_MI2S_RX, + LPI_MI2S_RX_0, 1, 1}, + [LPI_MI2S_TX_0] = { AFE_PORT_ID_INT0_MI2S_TX, + LPI_MI2S_TX_0, 0, 1}, + [LPI_MI2S_RX_1] = { AFE_PORT_ID_INT1_MI2S_RX, + LPI_MI2S_RX_1, 1, 1}, + [LPI_MI2S_TX_1] = { AFE_PORT_ID_INT1_MI2S_TX, + LPI_MI2S_TX_1, 0, 1}, + [LPI_MI2S_RX_2] = { AFE_PORT_ID_INT2_MI2S_RX, + LPI_MI2S_RX_2, 1, 1}, + [LPI_MI2S_TX_2] = { AFE_PORT_ID_INT2_MI2S_TX, + LPI_MI2S_TX_2, 0, 1}, + [LPI_MI2S_RX_3] = { AFE_PORT_ID_INT3_MI2S_RX, + LPI_MI2S_RX_3, 1, 1}, + [LPI_MI2S_TX_3] = { AFE_PORT_ID_INT3_MI2S_TX, + LPI_MI2S_TX_3, 0, 1}, + [LPI_MI2S_RX_4] = { AFE_PORT_ID_INT4_MI2S_RX, + LPI_MI2S_RX_4, 1, 1}, + [LPI_MI2S_TX_4] = { AFE_PORT_ID_INT4_MI2S_TX, + LPI_MI2S_TX_4, 0, 1}, + [LPI_MI2S_RX_5] = { AFE_PORT_ID_INT5_MI2S_RX, + LPI_MI2S_RX_5, 1, 1}, + [LPI_MI2S_TX_5] = { AFE_PORT_ID_INT5_MI2S_TX, + LPI_MI2S_TX_5, 0, 1}, + [LPI_MI2S_RX_6] = { AFE_PORT_ID_INT6_MI2S_RX, + LPI_MI2S_RX_6, 1, 1}, + [LPI_MI2S_TX_6] = { AFE_PORT_ID_INT6_MI2S_TX, + LPI_MI2S_TX_6, 0, 1}, }; static void q6afe_port_free(struct kref *ref) @@ -1790,6 +1832,20 @@ struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id) case AFE_PORT_ID_QUATERNARY_MI2S_TX: case AFE_PORT_ID_QUINARY_MI2S_RX: case AFE_PORT_ID_QUINARY_MI2S_TX: + case AFE_PORT_ID_INT0_MI2S_RX: + case AFE_PORT_ID_INT0_MI2S_TX: + case AFE_PORT_ID_INT1_MI2S_RX: + case AFE_PORT_ID_INT1_MI2S_TX: + case AFE_PORT_ID_INT2_MI2S_RX: + case AFE_PORT_ID_INT2_MI2S_TX: + case AFE_PORT_ID_INT3_MI2S_RX: + case AFE_PORT_ID_INT3_MI2S_TX: + case AFE_PORT_ID_INT4_MI2S_RX: + case AFE_PORT_ID_INT4_MI2S_TX: + case AFE_PORT_ID_INT5_MI2S_RX: + case AFE_PORT_ID_INT5_MI2S_TX: + case AFE_PORT_ID_INT6_MI2S_RX: + case AFE_PORT_ID_INT6_MI2S_TX: cfg_type = AFE_PARAM_ID_I2S_CONFIG; break; case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7: From 593ccfc7d910a9a69f11dccb27139783004b92c6 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Thu, 30 Jul 2026 13:43:46 -0400 Subject: [PATCH 32/37] FROMGIT: ASoC: qdsp6: q6afe-dai: add internal mi2s support The bindings for LPI MI2S ports, originally exclusive to q6apm, can be used for internal MI2S ports on q6afe. Add the internal MI2S ports found on the SDM660 internal sound card using the LPI MI2S bindings. Signed-off-by: Richard Acayan Reviewed-by: Srinivas Kandagatla Link: https://patch.msgid.link/20260730174353.108023-9-mailingradian@gmail.com Signed-off-by: Mark Brown (cherry picked from commit 0b494ae6a582b07c090839b8c62b931d6f4e2848) Signed-off-by: Ricardo Salveti --- sound/soc/qcom/qdsp6/q6afe-dai.c | 48 ++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/sound/soc/qcom/qdsp6/q6afe-dai.c b/sound/soc/qcom/qdsp6/q6afe-dai.c index 0f47aadaabe1..c2a3e17caab5 100644 --- a/sound/soc/qcom/qdsp6/q6afe-dai.c +++ b/sound/soc/qcom/qdsp6/q6afe-dai.c @@ -411,6 +411,8 @@ static int q6afe_dai_prepare(struct snd_pcm_substream *substream, break; case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: + case LPI_MI2S_RX_0 ... LPI_MI2S_TX_4: + case LPI_MI2S_RX_5 ... LPI_MI2S_TX_6: rc = q6afe_i2s_port_prepare(dai_data->port[dai->id], &dai_data->port_config[dai->id].i2s_cfg); if (rc < 0) { @@ -662,6 +664,21 @@ static const struct snd_soc_dapm_route q6afe_dapm_routes[] = { /* USB playback AFE port receives data for playback, hence use the RX port */ {"USB Playback", NULL, "USB_RX"}, + + {"LPI RX0 MI2S Playback", NULL, "LPI_MI2S_RX_0"}, + {"LPI_MI2S_TX_0", NULL, "LPI TX0 MI2S Capture"}, + {"LPI RX1 MI2S Playback", NULL, "LPI_MI2S_RX_1"}, + {"LPI_MI2S_TX_1", NULL, "LPI TX1 MI2S Capture"}, + {"LPI RX2 MI2S Playback", NULL, "LPI_MI2S_RX_2"}, + {"LPI_MI2S_TX_2", NULL, "LPI TX2 MI2S Capture"}, + {"LPI RX3 MI2S Playback", NULL, "LPI_MI2S_RX_3"}, + {"LPI_MI2S_TX_3", NULL, "LPI TX3 MI2S Capture"}, + {"LPI RX4 MI2S Playback", NULL, "LPI_MI2S_RX_4"}, + {"LPI_MI2S_TX_4", NULL, "LPI TX4 MI2S Capture"}, + {"LPI RX5 MI2S Playback", NULL, "LPI_MI2S_RX_5"}, + {"LPI_MI2S_TX_5", NULL, "LPI TX5 MI2S Capture"}, + {"LPI RX6 MI2S Playback", NULL, "LPI_MI2S_RX_6"}, + {"LPI_MI2S_TX_6", NULL, "LPI TX6 MI2S Capture"}, }; static int msm_dai_q6_dai_probe(struct snd_soc_dai *dai) @@ -1006,6 +1023,35 @@ static const struct snd_soc_dapm_widget q6afe_dai_widgets[] = { 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("USB_RX", NULL, 0, SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_AIF_IN("LPI_MI2S_RX_0", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("LPI_MI2S_TX_0", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("LPI_MI2S_RX_1", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("LPI_MI2S_TX_1", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("LPI_MI2S_RX_2", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("LPI_MI2S_TX_2", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("LPI_MI2S_RX_3", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("LPI_MI2S_TX_3", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("LPI_MI2S_RX_4", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("LPI_MI2S_TX_4", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("LPI_MI2S_RX_5", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("LPI_MI2S_TX_5", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("LPI_MI2S_RX_6", NULL, + 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("LPI_MI2S_TX_6", NULL, + 0, SND_SOC_NOPM, 0, 0), }; static const struct snd_soc_component_driver q6afe_dai_component = { @@ -1039,6 +1085,8 @@ static void of_q6afe_parse_dai_data(struct device *dev, /* MI2S specific properties */ case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: + case LPI_MI2S_RX_0 ... LPI_MI2S_TX_4: + case LPI_MI2S_RX_5 ... LPI_MI2S_TX_6: priv = &data->priv[id]; ret = of_property_read_variable_u32_array(node, "qcom,sd-lines", From 349874ec088aa03020a4faead26423f488304d0b Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Thu, 30 Jul 2026 13:43:47 -0400 Subject: [PATCH 33/37] FROMGIT: ASoC: qdsp6: q6routing: add lpi mi2s support Add the ASM-AFE routing for LPI MI2S ports which represent internal MI2S ports on SDM660. Signed-off-by: Richard Acayan Reviewed-by: Srinivas Kandagatla Link: https://patch.msgid.link/20260730174353.108023-10-mailingradian@gmail.com Signed-off-by: Mark Brown (cherry picked from commit 14d3cca9c2ed1ae0d647f109cfdf5d63f3f5be09) Signed-off-by: Ricardo Salveti --- sound/soc/qcom/qdsp6/q6routing.c | 78 +++++++++++++++++++++++++++++++- 1 file changed, 77 insertions(+), 1 deletion(-) diff --git a/sound/soc/qcom/qdsp6/q6routing.c b/sound/soc/qcom/qdsp6/q6routing.c index f49243daa517..db5f156469c2 100644 --- a/sound/soc/qcom/qdsp6/q6routing.c +++ b/sound/soc/qcom/qdsp6/q6routing.c @@ -127,7 +127,14 @@ { mix_name, "TX_CODEC_DMA_TX_2", "TX_CODEC_DMA_TX_2"}, \ { mix_name, "TX_CODEC_DMA_TX_3", "TX_CODEC_DMA_TX_3"}, \ { mix_name, "TX_CODEC_DMA_TX_4", "TX_CODEC_DMA_TX_4"}, \ - { mix_name, "TX_CODEC_DMA_TX_5", "TX_CODEC_DMA_TX_5"} + { mix_name, "TX_CODEC_DMA_TX_5", "TX_CODEC_DMA_TX_5"}, \ + { mix_name, "LPI_MI2S_TX_0", "LPI_MI2S_TX_0" }, \ + { mix_name, "LPI_MI2S_TX_1", "LPI_MI2S_TX_1" }, \ + { mix_name, "LPI_MI2S_TX_2", "LPI_MI2S_TX_2" }, \ + { mix_name, "LPI_MI2S_TX_3", "LPI_MI2S_TX_3" }, \ + { mix_name, "LPI_MI2S_TX_4", "LPI_MI2S_TX_4" }, \ + { mix_name, "LPI_MI2S_TX_5", "LPI_MI2S_TX_5" }, \ + { mix_name, "LPI_MI2S_TX_6", "LPI_MI2S_TX_6" } #define Q6ROUTING_TX_MIXERS(id) \ SOC_SINGLE_EXT("PRI_MI2S_TX", PRIMARY_MI2S_TX, \ @@ -320,6 +327,27 @@ id, 1, 0, msm_routing_get_audio_mixer, \ msm_routing_put_audio_mixer), \ SOC_SINGLE_EXT("TX_CODEC_DMA_TX_5", TX_CODEC_DMA_TX_5, \ + id, 1, 0, msm_routing_get_audio_mixer, \ + msm_routing_put_audio_mixer), \ + SOC_SINGLE_EXT("LPI_MI2S_TX_0", LPI_MI2S_TX_0, \ + id, 1, 0, msm_routing_get_audio_mixer, \ + msm_routing_put_audio_mixer), \ + SOC_SINGLE_EXT("LPI_MI2S_TX_1", LPI_MI2S_TX_1, \ + id, 1, 0, msm_routing_get_audio_mixer, \ + msm_routing_put_audio_mixer), \ + SOC_SINGLE_EXT("LPI_MI2S_TX_2", LPI_MI2S_TX_2, \ + id, 1, 0, msm_routing_get_audio_mixer, \ + msm_routing_put_audio_mixer), \ + SOC_SINGLE_EXT("LPI_MI2S_TX_3", LPI_MI2S_TX_3, \ + id, 1, 0, msm_routing_get_audio_mixer, \ + msm_routing_put_audio_mixer), \ + SOC_SINGLE_EXT("LPI_MI2S_TX_4", LPI_MI2S_TX_4, \ + id, 1, 0, msm_routing_get_audio_mixer, \ + msm_routing_put_audio_mixer), \ + SOC_SINGLE_EXT("LPI_MI2S_TX_5", LPI_MI2S_TX_5, \ + id, 1, 0, msm_routing_get_audio_mixer, \ + msm_routing_put_audio_mixer), \ + SOC_SINGLE_EXT("LPI_MI2S_TX_6", LPI_MI2S_TX_6, \ id, 1, 0, msm_routing_get_audio_mixer, \ msm_routing_put_audio_mixer), @@ -711,6 +739,26 @@ static const struct snd_kcontrol_new rxcodec_dma_rx_6_mixer_controls[] = { static const struct snd_kcontrol_new rx_codec_dma_rx_7_mixer_controls[] = { Q6ROUTING_RX_MIXERS(RX_CODEC_DMA_RX_7) }; +static const struct snd_kcontrol_new lpi_mi2s_rx_0_mixer_controls[] = { + Q6ROUTING_RX_MIXERS(LPI_MI2S_RX_0) }; + +static const struct snd_kcontrol_new lpi_mi2s_rx_1_mixer_controls[] = { + Q6ROUTING_RX_MIXERS(LPI_MI2S_RX_1) }; + +static const struct snd_kcontrol_new lpi_mi2s_rx_2_mixer_controls[] = { + Q6ROUTING_RX_MIXERS(LPI_MI2S_RX_2) }; + +static const struct snd_kcontrol_new lpi_mi2s_rx_3_mixer_controls[] = { + Q6ROUTING_RX_MIXERS(LPI_MI2S_RX_3) }; + +static const struct snd_kcontrol_new lpi_mi2s_rx_4_mixer_controls[] = { + Q6ROUTING_RX_MIXERS(LPI_MI2S_RX_4) }; + +static const struct snd_kcontrol_new lpi_mi2s_rx_5_mixer_controls[] = { + Q6ROUTING_RX_MIXERS(LPI_MI2S_RX_5) }; + +static const struct snd_kcontrol_new lpi_mi2s_rx_6_mixer_controls[] = { + Q6ROUTING_RX_MIXERS(LPI_MI2S_RX_6) }; static const struct snd_kcontrol_new mmul1_mixer_controls[] = { Q6ROUTING_TX_MIXERS(MSM_FRONTEND_DAI_MULTIMEDIA1) }; @@ -940,6 +988,27 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_DAPM_MIXER("USB_RX Audio Mixer", SND_SOC_NOPM, 0, 0, usb_rx_mixer_controls, ARRAY_SIZE(usb_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("LPI_MI2S_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + lpi_mi2s_rx_0_mixer_controls, + ARRAY_SIZE(lpi_mi2s_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("LPI_MI2S_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + lpi_mi2s_rx_1_mixer_controls, + ARRAY_SIZE(lpi_mi2s_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("LPI_MI2S_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + lpi_mi2s_rx_2_mixer_controls, + ARRAY_SIZE(lpi_mi2s_rx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("LPI_MI2S_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + lpi_mi2s_rx_3_mixer_controls, + ARRAY_SIZE(lpi_mi2s_rx_3_mixer_controls)), + SND_SOC_DAPM_MIXER("LPI_MI2S_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0, + lpi_mi2s_rx_4_mixer_controls, + ARRAY_SIZE(lpi_mi2s_rx_4_mixer_controls)), + SND_SOC_DAPM_MIXER("LPI_MI2S_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0, + lpi_mi2s_rx_5_mixer_controls, + ARRAY_SIZE(lpi_mi2s_rx_5_mixer_controls)), + SND_SOC_DAPM_MIXER("LPI_MI2S_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0, + lpi_mi2s_rx_6_mixer_controls, + ARRAY_SIZE(lpi_mi2s_rx_6_mixer_controls)), SND_SOC_DAPM_MIXER("MultiMedia1 Mixer", SND_SOC_NOPM, 0, 0, mmul1_mixer_controls, ARRAY_SIZE(mmul1_mixer_controls)), SND_SOC_DAPM_MIXER("MultiMedia2 Mixer", SND_SOC_NOPM, 0, 0, @@ -1033,6 +1102,13 @@ static const struct snd_soc_dapm_route intercon[] = { Q6ROUTING_RX_DAPM_ROUTE("RX_CODEC_DMA_RX_6 Audio Mixer", "RX_CODEC_DMA_RX_6"), Q6ROUTING_RX_DAPM_ROUTE("RX_CODEC_DMA_RX_7 Audio Mixer", "RX_CODEC_DMA_RX_7"), Q6ROUTING_RX_DAPM_ROUTE("USB_RX Audio Mixer", "USB_RX"), + Q6ROUTING_RX_DAPM_ROUTE("LPI_MI2S_RX_0 Audio Mixer", "LPI_MI2S_RX_0"), + Q6ROUTING_RX_DAPM_ROUTE("LPI_MI2S_RX_1 Audio Mixer", "LPI_MI2S_RX_1"), + Q6ROUTING_RX_DAPM_ROUTE("LPI_MI2S_RX_2 Audio Mixer", "LPI_MI2S_RX_2"), + Q6ROUTING_RX_DAPM_ROUTE("LPI_MI2S_RX_3 Audio Mixer", "LPI_MI2S_RX_3"), + Q6ROUTING_RX_DAPM_ROUTE("LPI_MI2S_RX_4 Audio Mixer", "LPI_MI2S_RX_4"), + Q6ROUTING_RX_DAPM_ROUTE("LPI_MI2S_RX_5 Audio Mixer", "LPI_MI2S_RX_5"), + Q6ROUTING_RX_DAPM_ROUTE("LPI_MI2S_RX_6 Audio Mixer", "LPI_MI2S_RX_6"), Q6ROUTING_TX_DAPM_ROUTE("MultiMedia1 Mixer"), Q6ROUTING_TX_DAPM_ROUTE("MultiMedia2 Mixer"), Q6ROUTING_TX_DAPM_ROUTE("MultiMedia3 Mixer"), From 9595731c33c2e5db05b7cd958a6ad8719f77574a Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 31 Jul 2026 17:26:26 +0100 Subject: [PATCH 34/37] BACKPORT: ASoC: qcom: sc8280xp: add monaco/monza controls for qcs8275 Update dai-ids and add DAPM widgets, sysclk and controls required for the VENTUNO-Q platform which uses MAX98090 codec. Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20260731162626.1588561-5-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Mark Brown (cherry picked from commit 4ba2678ad03ea21e946395d4b1476e9fb0d218fb) [rsalveti: keep this branch's struct snd_soc_common name and its shikra widget/control blocks, and keep the existing unchecked snd_soc_dai_set_fmt() call rather than adding error handling that would change behaviour for every other board using this machine driver] Signed-off-by: Ricardo Salveti --- sound/soc/qcom/sc8280xp.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c index b18996e41227..083515feabe9 100644 --- a/sound/soc/qcom/sc8280xp.c +++ b/sound/soc/qcom/sc8280xp.c @@ -37,6 +37,26 @@ static struct snd_soc_dapm_widget sc8280xp_dapm_widgets[] = { SND_SOC_DAPM_SPK("DP7 Jack", NULL), }; +static const struct snd_kcontrol_new max98090_controls[] = { + SOC_DAPM_PIN_SWITCH("Headset Mic12"), + SOC_DAPM_PIN_SWITCH("Headphone"), + SOC_DAPM_PIN_SWITCH("Headset Mic56"), + SOC_DAPM_PIN_SWITCH("Speaker"), + SOC_DAPM_PIN_SWITCH("Receiver"), + SOC_DAPM_PIN_SWITCH("Int Mic"), +}; + +static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = { + SND_SOC_DAPM_HP("Headphone Jack", NULL), + SND_SOC_DAPM_MIC("Mic Jack", NULL), + SND_SOC_DAPM_HP("Headphone", NULL), + SND_SOC_DAPM_MIC("Headset Mic12", NULL), + SND_SOC_DAPM_MIC("Headset Mic56", NULL), + SND_SOC_DAPM_MIC("Int Mic", NULL), + SND_SOC_DAPM_SPK("Receiver", NULL), + SND_SOC_DAPM_SPK("Speaker", NULL), +}; + static struct snd_soc_dapm_widget shikra_cqm_dapm_widgets[] = { SND_SOC_DAPM_HP("Headphone Jack", NULL), SND_SOC_DAPM_MIC("Mic Jack", NULL), @@ -258,6 +278,7 @@ static int sc8280xp_snd_hw_params(struct snd_pcm_substream *substream, switch (cpu_dai->id) { case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: + case LPI_MI2S_RX_0 ... LPI_MI2S_TX_4: snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP); if (pdata->snd_soc_common_priv->codec_dai_fmt) @@ -398,8 +419,12 @@ static struct snd_soc_common qcs6490_priv_data = { static struct snd_soc_common qcs8275_priv_data = { .driver_name = "qcs8300", - .dapm_widgets = sc8280xp_dapm_widgets, - .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), + .dapm_widgets = max98090_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(max98090_dapm_widgets), + .controls = max98090_controls, + .num_controls = ARRAY_SIZE(max98090_controls), + .codec_sysclk_set = true, + .codec_dai_fmt = SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_BC_FC, }; static struct snd_soc_common sc8280xp_priv_data = { From 57d0839704febb9a443a75bd5ee839c919f69419 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Mon, 29 Jun 2026 21:22:55 +0200 Subject: [PATCH 35/37] FROMGIT: clk: qcom: gcc-qcs8300: Use retention for PCIe power domains As the PCIe host controller driver does not yet support dealing with the loss of state during suspend, use retention for relevant GDSCs. Fix the PCIe link not surviving upon resume, and GDSC error: gcc_pcie_0_gdsc status stuck at 'off' Fixes: 95eeb2ffce73 ("clk: qcom: Add support for Global Clock Controller on QCS8300") Signed-off-by: Loic Poulain Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260629-monza-suspend-v1-1-b601d8a2f2f8@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 11b170abe4d324cac0d15a410282d1ec2b6bafa0) Signed-off-by: Ricardo Salveti --- drivers/clk/qcom/gcc-qcs8300.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs8300.c b/drivers/clk/qcom/gcc-qcs8300.c index 7a7f4eca40d8..fe0632687f9f 100644 --- a/drivers/clk/qcom/gcc-qcs8300.c +++ b/drivers/clk/qcom/gcc-qcs8300.c @@ -3268,7 +3268,7 @@ static struct gdsc gcc_pcie_0_gdsc = { .pd = { .name = "gcc_pcie_0_gdsc", }, - .pwrsts = PWRSTS_OFF_ON, + .pwrsts = PWRSTS_RET_ON, .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR, }; @@ -3282,7 +3282,7 @@ static struct gdsc gcc_pcie_1_gdsc = { .pd = { .name = "gcc_pcie_1_gdsc", }, - .pwrsts = PWRSTS_OFF_ON, + .pwrsts = PWRSTS_RET_ON, .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR, }; From 4c5e56627506919b41ffb8c3e43333a5fc7b5ec9 Mon Sep 17 00:00:00 2001 From: Faruque Ansari Date: Mon, 16 Mar 2026 16:07:52 +0530 Subject: [PATCH 36/37] UPSTREAM: cpufreq: Add QCS8300 to cpufreq-dt-platdev blocklist The Qualcomm QCS8300 platform uses the qcom-cpufreq-hw driver, so add it to the cpufreq-dt-platdev driver's blocklist. Signed-off-by: Faruque Ansari Reviewed-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Viresh Kumar (cherry picked from commit d6f8e0e06dee066076a45eea4f9f85247f85477d) Link: https://lore.kernel.org/r/20260316103752.289324-1-faruque.ansari@oss.qualcomm.com [rsalveti: add the Link: trailer, which the upstream commit is missing] Signed-off-by: Ricardo Salveti --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index 47dd76acd31e..6a1470065814 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -157,6 +157,7 @@ static const struct of_device_id blocklist[] __initconst = { { .compatible = "qcom,qcm2290", }, { .compatible = "qcom,qcm6490", }, { .compatible = "qcom,qcs404", }, + { .compatible = "qcom,qcs8300", }, { .compatible = "qcom,qdu1000", }, { .compatible = "qcom,sa8155p" }, { .compatible = "qcom,sa8540p" }, From 2929fcd7a37e1800de368ff880e81445a283c13f Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 13 Mar 2026 10:38:22 +0000 Subject: [PATCH 37/37] BACKPORT: arm64: defconfig: Enable configs for Arduino VENTUNO Q Enable ETHERNET PHY and Analog codec configs required for Arduino VENTUNO Q board. Signed-off-by: Srinivas Kandagatla Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260313103824.2634519-8-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson (cherry picked from commit 56f809222ea762f38f58e01d09aa58f0f3c4b788) [rsalveti: add CONFIG_QCA808X_PHY only; CONFIG_SND_SOC_MAX98090=m is already enabled on this branch] Signed-off-by: Ricardo Salveti --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f2d30d8ee470..0bb70c07bbbc 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -408,6 +408,7 @@ CONFIG_MARVELL_88Q2XXX_PHY=y CONFIG_MICREL_PHY=y CONFIG_MICROSEMI_PHY=y CONFIG_AT803X_PHY=y +CONFIG_QCA808X_PHY=m CONFIG_REALTEK_PHY=y CONFIG_ROCKCHIP_PHY=y CONFIG_DP83867_PHY=y