From 2ff3702f8a408fd01a486b651f3e876f3280d9e0 Mon Sep 17 00:00:00 2001 From: Ajinkya Inchure Date: Fri, 28 Aug 2026 18:20:16 +0530 Subject: [PATCH 1/2] arm64: dts: qcom: fix checkpath for talos files For talos.dtsi, talos-lyra-evk.dts, talos-lyra-evk-som.dtsi files checkpath was returning errors. Fixed them all together Signed-off-by: Ajinkya Inchure --- .../boot/dts/qcom/talos-lyra-evk-som.dtsi | 18 +- arch/arm64/boot/dts/qcom/talos-lyra-evk.dts | 14 +- arch/arm64/boot/dts/qcom/talos.dtsi | 868 +++++++++--------- 3 files changed, 450 insertions(+), 450 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi index f21dc568a5b75..d4f8c0bd243de 100644 --- a/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi @@ -234,14 +234,14 @@ wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; iommu-map = <0x0 &apps_smmu 0x400 0x1>, - <0x100 &apps_smmu 0x401 0x1>, - <0x208 &apps_smmu 0x402 0x1>, - <0x210 &apps_smmu 0x403 0x1>, - <0x218 &apps_smmu 0x404 0x1>, - <0x300 &apps_smmu 0x405 0x1>, - <0x400 &apps_smmu 0x406 0x1>, - <0x500 &apps_smmu 0x407 0x1>, - <0x501 &apps_smmu 0x408 0x1>; + <0x100 &apps_smmu 0x401 0x1>, + <0x208 &apps_smmu 0x402 0x1>, + <0x210 &apps_smmu 0x403 0x1>, + <0x218 &apps_smmu 0x404 0x1>, + <0x300 &apps_smmu 0x405 0x1>, + <0x400 &apps_smmu 0x406 0x1>, + <0x500 &apps_smmu 0x407 0x1>, + <0x501 &apps_smmu 0x408 0x1>; status = "okay"; }; @@ -346,6 +346,7 @@ }; &tlmm { + pcie_default_state: pcie-default-state { clkreq-pins { pins = "gpio90"; @@ -373,4 +374,3 @@ &uart0 { status = "okay"; }; - diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts index 6292e6dd5842a..b83c2ccf3d1b7 100644 --- a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts @@ -11,7 +11,7 @@ / { model = "Qualcomm QCS615 Talos lyra EVK"; compatible = "qcom,talos-lyra-evk", "qcom,talos-lyra-evk-som", "qcom,qcs615", - "qcom,sm6150"; + "qcom,sm6150"; chassis-type = "embedded"; aliases { @@ -160,13 +160,13 @@ }; &spi6 { - status = "okay"; + status = "okay"; - tpm@0 { - compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; - reg = <0>; - spi-max-frequency = <20000000>; - }; + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index fb1bbc51bb8a4..e472408e01ef8 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -50,10 +50,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -75,10 +75,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_100: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -100,10 +100,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_200: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -125,10 +125,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_300: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -150,10 +150,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_400: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -175,10 +175,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_500: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -201,10 +201,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_600: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -226,10 +226,10 @@ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_700: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -635,8 +635,8 @@ cluster_pd: power-domain-cluster { #power-domain-cells = <0>; domain-idle-states = <&cluster_sleep_0 - &cluster_sleep_1 - &cluster_sleep_2>; + &cluster_sleep_1 + &cluster_sleep_2>; }; }; @@ -693,8 +693,8 @@ <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; clock-names = "bi_tcxo", - "bi_tcxo_ao", - "sleep_clk"; + "bi_tcxo_ao", + "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; @@ -721,14 +721,14 @@ sdhc_1: mmc@7c4000 { compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0 0x007c4000 0x0 0x1000>, - <0x0 0x007c5000 0x0 0x1000>, - <0x0 0x007c8000 0x0 0x8000>; + <0x0 0x007c5000 0x0 0x1000>, + <0x0 0x007c8000 0x0 0x8000>; reg-names = "hc", - "cqhci", - "ice"; + "cqhci", + "ice"; interrupts = , - ; + ; interrupt-names = "hc_irq", "pwr_irq"; @@ -737,9 +737,9 @@ <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface", - "core", - "xo", - "ice"; + "core", + "xo", + "ice"; resets = <&gcc GCC_SDCC1_BCR>; @@ -751,7 +751,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "sdhc-ddr", - "cpu-sdhc"; + "cpu-sdhc"; qcom,dll-config = <0x000f642c>; qcom,ddr-config = <0x80040868>; @@ -790,13 +790,13 @@ reg = <0x0 0x800000 0x0 0x60000>; #dma-cells = <3>; interrupts = , - , - , - , - , - , - , - ; + , + , + , + , + , + , + ; dma-channels = <8>; dma-channel-mask = <0xf>; iommus = <&apps_smmu 0xd6 0x0>; @@ -810,7 +810,7 @@ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; clock-names = "m-ahb", - "s-ahb"; + "s-ahb"; iommus = <&apps_smmu 0xc3 0x0>; #address-cells = <2>; #size-cells = <2>; @@ -829,7 +829,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; @@ -852,14 +852,14 @@ <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + "qup-config", + "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, - <&gpi_dma0 1 1 QCOM_GPI_I2C>; + <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -880,14 +880,14 @@ <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + "qup-config", + "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, - <&gpi_dma0 1 2 QCOM_GPI_I2C>; + <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -904,13 +904,13 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, - <&gpi_dma0 1 2 QCOM_GPI_SPI>; + <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names = "tx", - "rx"; + "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -923,14 +923,14 @@ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, - <&qup_uart2_tx>, <&qup_uart2_rx>; + <&qup_uart2_tx>, <&qup_uart2_rx>; pinctrl-names = "default"; interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; @@ -953,14 +953,14 @@ <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + "qup-config", + "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, - <&gpi_dma0 1 3 QCOM_GPI_I2C>; + <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; }; @@ -970,13 +970,13 @@ reg = <0x0 0xa00000 0x0 0x60000>; #dma-cells = <3>; interrupts = , - , - , - , - , - , - , - ; + , + , + , + , + , + , + ; dma-channels = <8>; dma-channel-mask = <0xf>; iommus = <&apps_smmu 0x376 0x0>; @@ -990,7 +990,7 @@ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; clock-names = "m-ahb", - "s-ahb"; + "s-ahb"; iommus = <&apps_smmu 0x363 0x0>; #address-cells = <2>; #size-cells = <2>; @@ -1013,14 +1013,14 @@ <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + "qup-config", + "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, - <&gpi_dma1 1 0 QCOM_GPI_I2C>; + <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -1039,13 +1039,13 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, - <&gpi_dma1 1 0 QCOM_GPI_SPI>; + <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -1055,7 +1055,7 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, - <&qup_uart4_tx>, <&qup_uart4_rx>; + <&qup_uart4_tx>, <&qup_uart4_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1063,7 +1063,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; @@ -1086,14 +1086,14 @@ <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + "qup-config", + "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, - <&gpi_dma1 1 1 QCOM_GPI_I2C>; + <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -1114,14 +1114,14 @@ <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + "qup-config", + "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, - <&gpi_dma1 1 2 QCOM_GPI_I2C>; + <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -1140,13 +1140,13 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, - <&gpi_dma1 1 2 QCOM_GPI_SPI>; + <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -1156,7 +1156,7 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, - <&qup_uart6_tx>, <&qup_uart6_rx>; + <&qup_uart6_tx>, <&qup_uart6_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1164,7 +1164,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; @@ -1187,14 +1187,14 @@ <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + "qup-config", + "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, - <&gpi_dma1 1 3 QCOM_GPI_I2C>; + <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -1213,13 +1213,13 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, - <&gpi_dma1 1 3 QCOM_GPI_SPI>; + <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names = "tx", - "rx"; + "rx"; status = "disabled"; }; @@ -1229,7 +1229,7 @@ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, - <&qup_uart7_tx>, <&qup_uart7_rx>; + <&qup_uart7_tx>, <&qup_uart7_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1237,7 +1237,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", - "qup-config"; + "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; @@ -1280,17 +1280,17 @@ device_type = "pci"; compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150"; reg = <0x0 0x01c08000 0x0 0x3000>, - <0x0 0x40000000 0x0 0xf1d>, - <0x0 0x40000f20 0x0 0xa8>, - <0x0 0x40001000 0x0 0x1000>, - <0x0 0x40100000 0x0 0x100000>, - <0x0 0x01c0b000 0x0 0x1000>; + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c0b000 0x0 0x1000>; reg-names = "parf", - "dbi", - "elbi", - "atu", - "config", - "mhi"; + "dbi", + "elbi", + "atu", + "config", + "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, @@ -1303,14 +1303,14 @@ num-lanes = <1>; interrupts = , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1335,11 +1335,11 @@ <&gcc GCC_PCIE_0_SLV_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a"; + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; assigned-clock-rates = <19200000>; @@ -1350,7 +1350,7 @@ interconnect-names = "pcie-mem", "cpu-pcie"; iommu-map = <0x0 &apps_smmu 0x400 0x1>, - <0x100 &apps_smmu 0x401 0x1>; + <0x100 &apps_smmu 0x401 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -1404,10 +1404,10 @@ <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "aux", - "cfg_ahb", - "ref", - "refgen", - "pipe"; + "cfg_ahb", + "ref", + "refgen", + "pipe"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; @@ -1426,9 +1426,9 @@ ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>, - <0x0 0x01d90000 0x0 0x8000>; + <0x0 0x01d90000 0x0 0x8000>; reg-names = "std", - "ice"; + "ice"; interrupts = ; @@ -1441,13 +1441,13 @@ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; clock-names = "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "ice_core_clk"; + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "ice_core_clk"; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; @@ -1458,7 +1458,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "ufs-ddr", - "cpu-ufs"; + "cpu-ufs"; power-domains = <&gcc UFS_PHY_GDSC>; @@ -1522,8 +1522,8 @@ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names = "ref", - "ref_aux", - "qref"; + "ref_aux", + "qref"; power-domains = <&gcc UFS_PHY_GDSC>; @@ -1573,11 +1573,11 @@ tlmm: pinctrl@3100000 { compatible = "qcom,qcs615-tlmm"; reg = <0x0 0x03100000 0x0 0x300000>, - <0x0 0x03500000 0x0 0x300000>, - <0x0 0x03d00000 0x0 0x300000>; + <0x0 0x03500000 0x0 0x300000>, + <0x0 0x03d00000 0x0 0x300000>; reg-names = "east", - "west", - "south"; + "west", + "south"; interrupts = ; gpio-ranges = <&tlmm 0 0 124>; gpio-controller; @@ -1952,11 +1952,11 @@ gpu: gpu@5000000 { compatible = "qcom,adreno-612.0", "qcom,adreno"; reg = <0x0 0x05000000 0x0 0x40000>, - <0x0 0x0509e000 0x0 0x1000>, - <0x0 0x05061000 0x0 0x800>; + <0x0 0x0509e000 0x0 0x1000>, + <0x0 0x05061000 0x0 0x800>; reg-names = "kgsl_3d0_reg_memory", - "cx_mem", - "cx_dbgc"; + "cx_mem", + "cx_dbgc"; clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>; clock-names = "core"; @@ -2027,18 +2027,18 @@ <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = "gmu", - "cxo", - "axi", - "memnoc", - "smmu_vote"; + "cxo", + "axi", + "memnoc", + "smmu_vote"; power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; power-domain-names = "cx", - "gx"; + "gx"; interrupts = , - ; + ; interrupt-names = "oob", "gmu"; @@ -2069,25 +2069,25 @@ adreno_smmu: iommu@50a0000 { compatible = "qcom,qcs615-smmu-500", "qcom,adreno-smmu", - "qcom,smmu-500", "arm,mmu-500"; + "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x050a0000 0x0 0x40000>; #iommu-cells = <2>; #global-interrupts = <1>; interrupts = , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + ; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; clock-names = "mem", - "hlos", - "iface"; + "hlos", + "iface"; power-domains = <&gpucc CX_GDSC>; dma-coherent; }; @@ -2095,9 +2095,9 @@ stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x06002000 0x0 0x1000>, - <0x0 0x16280000 0x0 0x180000>; + <0x0 0x16280000 0x0 0x180000>; reg-names = "stm-base", - "stm-stimulus-base"; + "stm-stimulus-base"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3749,10 +3749,10 @@ reg = <0x0 0x08300000 0x0 0x4040>; interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", @@ -3910,7 +3910,7 @@ reg-names = "hc"; interrupts = , - ; + ; interrupt-names = "hc_irq", "pwr_irq"; @@ -3918,8 +3918,8 @@ <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", - "core", - "xo"; + "core", + "xo"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; @@ -3930,7 +3930,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "sdhc-ddr", - "cpu-sdhc"; + "cpu-sdhc"; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; @@ -3960,7 +3960,7 @@ qspi: spi@88df000 { compatible = "qcom,qcs615-qspi", - "qcom,qspi-v1"; + "qcom,qspi-v1"; reg = <0x0 0x088df000 0x0 0x1000>; interrupts = ; @@ -3968,14 +3968,14 @@ clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <&gcc GCC_QSPI_CORE_CLK>; clock-names = "iface", - "core"; + "core"; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_QSPI QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qspi-config", - "qspi-memory"; + "qspi-memory"; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qspi_opp_table>; @@ -4001,9 +4001,9 @@ llcc: system-cache-controller@9200000 { compatible = "qcom,qcs615-llcc"; reg = <0x0 0x09200000 0x0 0x50000>, - <0x0 0x09600000 0x0 0x50000>; + <0x0 0x09600000 0x0 0x50000>; reg-names = "llcc0_base", - "llcc_broadcast_base"; + "llcc_broadcast_base"; }; gem_noc: interconnect@9680000 { @@ -4024,17 +4024,17 @@ <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; clock-names = "core", - "iface", - "bus", - "vcodec0_core", - "vcodec0_bus"; + "iface", + "bus", + "vcodec0_core", + "vcodec0_bus"; power-domains = <&videocc VENUS_GDSC>, <&videocc VCODEC0_GDSC>, <&rpmhpd RPMHPD_CX>; power-domain-names = "venus", - "vcodec0", - "cx"; + "vcodec0", + "cx"; operating-points-v2 = <&venus_opp_table>; @@ -4043,7 +4043,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "video-mem", - "cpu-cfg"; + "cpu-cfg"; iommus = <&apps_smmu 0xe60 0x20>; @@ -4108,8 +4108,8 @@ <&camcc CAM_CC_CPAS_AHB_CLK>, <&camcc CAM_CC_CCI_CLK>; clock-names = "camnoc_axi", - "cpas_ahb", - "cci"; + "cpas_ahb", + "cci"; pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>; pinctrl-names = "default"; @@ -4137,45 +4137,45 @@ compatible = "qcom,sm6150-camss"; reg = <0x0 0x0acb3000 0x0 0x1000>, - <0x0 0x0acba000 0x0 0x1000>, - <0x0 0x0acc8000 0x0 0x1000>, - <0x0 0x0ac65000 0x0 0x1000>, - <0x0 0x0ac66000 0x0 0x1000>, - <0x0 0x0ac67000 0x0 0x1000>, - <0x0 0x0acaf000 0x0 0x4000>, - <0x0 0x0acb6000 0x0 0x4000>, - <0x0 0x0acc4000 0x0 0x4000>, - <0x0 0x0ac6f000 0x0 0x3000>, - <0x0 0x0ac42000 0x0 0x5000>, - <0x0 0x0ac48000 0x0 0x1000>, - <0x0 0x0ac40000 0x0 0x1000>, - <0x0 0x0ac18000 0x0 0x3000>, - <0x0 0x0ac00000 0x0 0x6000>, - <0x0 0x0ac10000 0x0 0x8000>, - <0x0 0x0ac87000 0x0 0x3000>, - <0x0 0x0ac52000 0x0 0x4000>, - <0x0 0x0ac4e000 0x0 0x4000>, - <0x0 0x0ac6b000 0x0 0x0a00>; + <0x0 0x0acba000 0x0 0x1000>, + <0x0 0x0acc8000 0x0 0x1000>, + <0x0 0x0ac65000 0x0 0x1000>, + <0x0 0x0ac66000 0x0 0x1000>, + <0x0 0x0ac67000 0x0 0x1000>, + <0x0 0x0acaf000 0x0 0x4000>, + <0x0 0x0acb6000 0x0 0x4000>, + <0x0 0x0acc4000 0x0 0x4000>, + <0x0 0x0ac6f000 0x0 0x3000>, + <0x0 0x0ac42000 0x0 0x5000>, + <0x0 0x0ac48000 0x0 0x1000>, + <0x0 0x0ac40000 0x0 0x1000>, + <0x0 0x0ac18000 0x0 0x3000>, + <0x0 0x0ac00000 0x0 0x6000>, + <0x0 0x0ac10000 0x0 0x8000>, + <0x0 0x0ac87000 0x0 0x3000>, + <0x0 0x0ac52000 0x0 0x4000>, + <0x0 0x0ac4e000 0x0 0x4000>, + <0x0 0x0ac6b000 0x0 0x0a00>; reg-names = "csid0", - "csid1", - "csid_lite", - "csiphy0", - "csiphy1", - "csiphy2", - "vfe0", - "vfe1", - "vfe_lite", - "bps", - "camnoc", - "cpas_cdm", - "cpas_top", - "icp_csr", - "icp_qgic", - "icp_sierra", - "ipe0", - "jpeg_dma", - "jpeg_enc", - "lrme"; + "csid1", + "csid_lite", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite", + "bps", + "camnoc", + "cpas_cdm", + "cpas_top", + "icp_csr", + "icp_qgic", + "icp_sierra", + "ipe0", + "jpeg_dma", + "jpeg_enc", + "lrme"; clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&gcc GCC_CAMERA_HF_AXI_CLK>, @@ -4211,38 +4211,38 @@ <&camcc CAM_CC_JPEG_CLK>, <&camcc CAM_CC_LRME_CLK>; clock-names = "gcc_ahb", - "gcc_axi_hf", - "camnoc_axi", - "cpas_ahb", - "csiphy0", - "csiphy0_timer", - "csiphy1", - "csiphy1_timer", - "csiphy2", - "csiphy2_timer", - "soc_ahb", - "vfe0", - "vfe0_axi", - "vfe0_cphy_rx", - "vfe0_csid", - "vfe1", - "vfe1_axi", - "vfe1_cphy_rx", - "vfe1_csid", - "vfe_lite", - "vfe_lite_cphy_rx", - "vfe_lite_csid", - "bps", - "bps_ahb", - "bps_axi", - "bps_areg", - "icp", - "ipe0", - "ipe0_ahb", - "ipe0_areg", - "ipe0_axi", - "jpeg", - "lrme"; + "gcc_axi_hf", + "camnoc_axi", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "soc_ahb", + "vfe0", + "vfe0_axi", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1", + "vfe1_axi", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe_lite", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "bps", + "bps_ahb", + "bps_axi", + "bps_areg", + "icp", + "ipe0", + "ipe0_ahb", + "ipe0_areg", + "ipe0_axi", + "jpeg", + "lrme"; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, @@ -4253,25 +4253,25 @@ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "ahb", - "hf_0", - "hf_1", - "sf_mnoc"; + "hf_0", + "hf_1", + "sf_mnoc"; interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + ; interrupt-names = "csid0", "csid1", "csid_lite", @@ -4308,10 +4308,10 @@ <&camcc BPS_GDSC>, <&camcc IPE_0_GDSC>; power-domain-names = "ife0", - "ife1", - "top", - "bps", - "ipe"; + "ife1", + "top", + "bps", + "ipe"; status = "disabled"; @@ -4354,7 +4354,7 @@ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "mdp0-mem", - "cpu-cfg"; + "cpu-cfg"; power-domains = <&dispcc MDSS_CORE_GDSC>; @@ -4377,18 +4377,18 @@ mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm6150-dpu"; reg = <0x0 0x0ae01000 0x0 0x8f000>, - <0x0 0x0aeb0000 0x0 0x2008>; + <0x0 0x0aeb0000 0x0 0x2008>; reg-names = "mdp", - "vbif"; + "vbif"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "iface", - "bus", - "core", - "vsync"; + "bus", + "core", + "vsync"; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd RPMHPD_CX>; @@ -4440,10 +4440,10 @@ compatible = "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp"; reg = <0x0 0x0ae90000 0x0 0x200>, - <0x0 0x0ae90200 0x0 0x200>, - <0x0 0x0ae90400 0x0 0x600>, - <0x0 0x0ae90a00 0x0 0x600>, - <0x0 0x0ae91000 0x0 0x600>; + <0x0 0x0ae90200 0x0 0x200>, + <0x0 0x0ae90400 0x0 0x600>, + <0x0 0x0ae90a00 0x0 0x600>, + <0x0 0x0ae91000 0x0 0x600>; interrupt-parent = <&mdss>; interrupts = <12>; @@ -4455,11 +4455,11 @@ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_iface", - "core_aux", - "ctrl_link", - "ctrl_link_iface", - "stream_pixel", - "stream_1_pixel"; + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, @@ -4533,11 +4533,11 @@ <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>; clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; + "byte_intf", + "pixel", + "core", + "iface", + "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; @@ -4587,11 +4587,11 @@ mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,sm6150-dsi-phy-14nm"; reg = <0x0 0x0ae94400 0x0 0x100>, - <0x0 0x0ae94500 0x0 0x300>, - <0x0 0x0ae94800 0x0 0x124>; + <0x0 0x0ae94500 0x0 0x300>, + <0x0 0x0ae94800 0x0 0x124>; reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; + "dsi_phy_lane", + "dsi_pll"; #clock-cells = <1>; #phy-cells = <0>; @@ -4599,7 +4599,7 @@ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", - "ref"; + "ref"; status = "disabled"; }; @@ -4625,7 +4625,7 @@ pdc: interrupt-controller@b220000 { compatible = "qcom,qcs615-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, - <0x0 0x17c000f0 0x0 0x64>; + <0x0 0x17c000f0 0x0 0x64>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; interrupt-parent = <&intc>; #interrupt-cells = <2>; @@ -4668,84 +4668,84 @@ dma-coherent; interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c440000 0x0 0x1100>, - <0x0 0x0c600000 0x0 0x2000000>, - <0x0 0x0e600000 0x0 0x100000>, - <0x0 0x0e700000 0x0 0xa0000>, - <0x0 0x0c40a000 0x0 0x26000>; + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x100000>, + <0x0 0x0e700000 0x0 0xa0000>, + <0x0 0x0c40a000 0x0 0x26000>; reg-names = "core", - "chnls", - "obsrvr", - "intr", - "cnfg"; + "chnls", + "obsrvr", + "intr", + "cnfg"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "periph_irq"; interrupt-controller; @@ -4759,7 +4759,7 @@ intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ interrupts = ; #address-cells = <0>; #interrupt-cells = <4>; @@ -4780,7 +4780,7 @@ apss_shared: mailbox@17c00000 { compatible = "qcom,qcs615-apss-shared", - "qcom,sdm845-apss-shared"; + "qcom,sdm845-apss-shared"; reg = <0x0 0x17c00000 0x0 0x1000>; #mbox-cells = <1>; }; @@ -4801,10 +4801,10 @@ frame@17c21000 { reg = <0x17c21000 0x1000>, - <0x17c22000 0x1000>; + <0x17c22000 0x1000>; frame-number = <0>; interrupts = , - ; + ; }; frame@17c23000 { @@ -4853,15 +4853,15 @@ apps_rsc: rsc@18200000 { compatible = "qcom,rpmh-rsc"; reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; reg-names = "drv-0", - "drv-1", - "drv-2"; + "drv-1", + "drv-2"; interrupts = , - , - ; + , + ; qcom,drv-id = <2>; qcom,tcs-offset = <0xd00>; @@ -4968,7 +4968,7 @@ clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "cfg_ahb", - "ref"; + "ref"; resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; @@ -4986,9 +4986,9 @@ <&gcc GCC_AHB2PHY_WEST_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "aux", - "ref", - "cfg_ahb", - "pipe"; + "ref", + "cfg_ahb", + "pipe"; resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; @@ -5013,14 +5013,14 @@ <&gcc GCC_AHB2PHY_WEST_CLK>, <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>; clock-names = "aux", - "ref", - "cfg_ahb", - "pipe"; + "ref", + "cfg_ahb", + "pipe"; resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >, <&gcc GCC_USB3_DP_PHY_SEC_BCR>; reset-names = "phy_phy", - "dp_phy"; + "dp_phy"; #clock-cells = <1>; #phy-cells = <1>; @@ -5041,22 +5041,22 @@ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB3_PRIM_CLKREF_CLK>; clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "xo"; + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, - <&pdc 9 IRQ_TYPE_EDGE_BOTH>, - <&pdc 8 IRQ_TYPE_EDGE_BOTH>, - <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, + <&pdc 8 IRQ_TYPE_EDGE_BOTH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "dwc_usb3", "pwr_event", "hs_phy_irq", @@ -5099,21 +5099,21 @@ <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, <&gcc GCC_USB2_PRIM_CLKREF_CLK>; clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "xo"; + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, <&gcc GCC_USB20_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, - <&pdc 11 IRQ_TYPE_EDGE_BOTH>, - <&pdc 10 IRQ_TYPE_EDGE_BOTH>; + <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, + <&pdc 11 IRQ_TYPE_EDGE_BOTH>, + <&pdc 10 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "dwc_usb3", "pwr_event", "hs_phy_irq", @@ -5147,9 +5147,9 @@ tsens0: thermal-sensor@c263000 { compatible = "qcom,qcs615-tsens", "qcom,tsens-v2"; reg = <0x0 0x0c263000 0x0 0x1000>, - <0x0 0x0c222000 0x0 0x1000>; + <0x0 0x0c222000 0x0 0x1000>; interrupts = , - ; + ; interrupt-names = "uplow", "critical"; #qcom,sensors = <16>; #thermal-sensor-cells = <1>; @@ -5160,10 +5160,10 @@ reg = <0x0 0x62400000 0x0 0x4040>; interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING 0>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", @@ -5285,9 +5285,9 @@ arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = , - , - , - ; + , + , + ; }; thermal-zones { From 5036b208430c90fdfe44b29e7917c11fce57667c Mon Sep 17 00:00:00 2001 From: Ajinkya Inchure Date: Fri, 28 Aug 2026 18:38:10 +0530 Subject: [PATCH 2/2] arm64: dts: qcom: add Talos Lyra EVK DTS for ethernet changes Adding DTS changes for enabling ethernet on talos-lyra board with TI PHY being used Signed-off-by: Ajinkya Inchure --- .../boot/dts/qcom/talos-lyra-evk-som.dtsi | 92 +++++++++++++++++++ arch/arm64/boot/dts/qcom/talos-lyra-evk.dts | 7 ++ arch/arm64/boot/dts/qcom/talos.dtsi | 34 +++++++ 3 files changed, 133 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi index d4f8c0bd243de..6352f41f7f48d 100644 --- a/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi @@ -210,6 +210,57 @@ }; }; +ðernet { + pinctrl-0 = <ðernet_defaults>; + pinctrl-names = "default"; + + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + status = "okay"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-id2000.a231"; + reg = <0x7>; + + reset-gpios = <&tlmm 105 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + }; +}; + &gcc { clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, @@ -346,6 +397,47 @@ }; &tlmm { + ethernet_defaults: ethernet-defaults-state { + mdc-pins { + pins = "gpio113"; + function = "rgmii"; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio114"; + function = "rgmii"; + bias-pull-up; + }; + + phy-intr-pins { + pins = "gpio121"; + function = "gpio"; + bias-disable; + drive-strength = <8>; + }; + + phy-reset-pins { + pins = "gpio105"; + function = "gpio"; + bias-pull-up; + drive-strength = <16>; + }; + + rgmii-rx-pins { + pins = "gpio81", "gpio82", "gpio83", "gpio102", "gpio103", "gpio112"; + function = "rgmii"; + bias-disable; + drive-strength = <2>; + }; + + rgmii-tx-pins { + pins = "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97"; + function = "rgmii"; + bias-pull-up; + drive-strength = <16>; + }; + }; pcie_default_state: pcie-default-state { clkreq-pins { diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts index b83c2ccf3d1b7..9cf83551239d6 100644 --- a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts @@ -108,6 +108,13 @@ reg = <0x21>; #gpio-cells = <2>; gpio-controller; + + emac0_phy_en_hog: emac0-phy-en-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "emac0-phy-en"; + }; }; expander2: gpio@38 { diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index e472408e01ef8..344c16b385e0e 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -686,6 +686,40 @@ #address-cells = <2>; #size-cells = <2>; + ethernet: ethernet@20000 { + compatible = "qcom,qcs615-ethqos", "qcom,qcs404-ethqos"; + reg = <0x0 0x00020000 0x0 0x10000>, + <0x0 0x00036000 0x0 0x100>; + reg-names = "stmmaceth", + "rgmii"; + + clocks = <&gcc GCC_EMAC_AXI_CLK>, + <&gcc GCC_EMAC_SLV_AHB_CLK>, + <&gcc GCC_EMAC_PTP_CLK>, + <&gcc GCC_EMAC_RGMII_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "rgmii"; + + interrupts = , + ; + interrupt-names = "macirq", + "eth_lpi"; + + power-domains = <&gcc EMAC_GDSC>; + resets = <&gcc GCC_EMAC_BCR>; + + iommus = <&apps_smmu 0x1c0 0x0>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <20480>; + + status = "disabled"; + }; + gcc: clock-controller@100000 { compatible = "qcom,qcs615-gcc"; reg = <0 0x00100000 0 0x1f0000>;