Currently there's one Opcode enum which defines all the opcodes. This means it's possible to create nonsense instructions that should not ever appear in RISC-V code, such as opcodes for the wrong instruction format.
This should be split apart so each instruction format has a separate opcode enum, to get better type safety.
Currently there's one
Opcodeenum which defines all the opcodes. This means it's possible to create nonsense instructions that should not ever appear in RISC-V code, such as opcodes for the wrong instruction format.This should be split apart so each instruction format has a separate opcode enum, to get better type safety.