From 33f265fe8e659ffbd42e3948808ee12f74797406 Mon Sep 17 00:00:00 2001 From: Dmitrii Fedorov <256009718+dmitrii-f-t27@users.noreply.github.com> Date: Tue, 11 Aug 2026 18:49:23 +0700 Subject: [PATCH] Unbreak FPGA CI and correct unbacked hardware claims MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit bootstrap/src/main.rs:4937,4962 — both synth.ys writers (Docker branch and local-yosys branch) emitted `read_verilog {files}`, parsing the compiler's own output with the Verilog-2005 frontend. The Verilog backend deliberately emits SystemVerilog static casts (bootstrap/src/compiler.rs:5068, `format!("{}'({})", width, buf)`), so yosys aborted with "Static cast is only supported in SystemVerilog mode" on build/fpga/generated/uart.v. Switched both to `read_verilog -sv -DSIMULATION {files}`, matching the working invocation already used at bootstrap/src/suite.rs:859. .github/workflows/fpga-build.yml:327 — the fpga-bitstream job cloned upstream YosysHQ/nextpnr and configured it with -DARCH=xilinx, but upstream nextpnr has no xilinx architecture, so CMake rejected the arch and the job exited 1. Clone gatecat/nextpnr-xilinx instead; dropped the `-b nextpnr-0.8` tag (it does not exist on the fork) and updated the following `cd` to the new directory name. The build/ and `cp nextpnr-xilinx` steps already match the fork's binary name and needed no change. prjxray clones left untouched. README.md:60,61,70 — System Status advertised the FPGA end-to-end bitstream pipeline as GREEN. Per the GitHub API, fpga-build.yml has 881 runs: 36 success, 842 failure, 3 cancelled; last success 2026-04-14; fpga-bitstream is skipped because its `needs: fpga-synthesis` never passes. Downgraded the three rows to RED with the measured numbers and the last-green date, while noting the local gen-verilog smoke still passes 5/5. specs/numeric/formats_catalog.t27:228 — the gf16 row cited Zenodo DOI 10.5281/zenodo.19227877 as its standard/source. That record is "Trinity B007: VSA Operations for Ternary Computing v5.0", resource type Software, a single 2.0 kB file with no FPGA frequency and no design, so it backs neither the standard nor the "323 MHz" claim. Dropped the "FPGA 35/35 at 323 MHz Artix-7" clause and the zenodo reference; source now cites specs/numeric/gf16.t27, which exists in this repo. All other fields unchanged. docs/arxiv-submission/trinity-gf16.tex:296 — XC7A100T LUT count was given as 126,800, which is the part's flip-flop count; corrected to 63,400. docs/arxiv-trinity-gf16-draft.md:116 — same correction. Deferred: the spiOverJtag bitstream rename is not included; it involves binary files and a .gz regeneration and is left for the maintainer. --- .github/workflows/fpga-build.yml | 4 ++-- README.md | 6 +++--- bootstrap/src/main.rs | 4 ++-- docs/arxiv-submission/trinity-gf16.tex | 2 +- docs/arxiv-trinity-gf16-draft.md | 2 +- specs/numeric/formats_catalog.t27 | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/.github/workflows/fpga-build.yml b/.github/workflows/fpga-build.yml index 63fed6f2e0..51f9d9336a 100644 --- a/.github/workflows/fpga-build.yml +++ b/.github/workflows/fpga-build.yml @@ -324,8 +324,8 @@ jobs: run: | if [ ! -f ~/.local/bin/nextpnr-xilinx ]; then cd ~ - git clone https://github.com/YosysHQ/nextpnr.git -b nextpnr-0.8 - cd nextpnr + git clone https://github.com/gatecat/nextpnr-xilinx.git + cd nextpnr-xilinx mkdir build && cd build cmake .. -DARCH=xilinx -DUSE_OPENMP=OFF make -j4 diff --git a/README.md b/README.md index 79c2ddb7a2..7f194fe736 100644 --- a/README.md +++ b/README.md @@ -57,8 +57,8 @@ Discoverability mirror of the numeric corpus. GitHub remains the primary source | Compiler | `t27c parse` | GREEN | 170+ specs parse | | Compiler | `t27c gen-verilog` | GREEN | 5/5 FPGA modules synthesize | | Compiler | `t27c seal` | GREEN | 170+ seals in `.trinity/seals/` | -| FPGA | Yosys synthesis | GREEN | 5/5 modules pass synth_xilinx | -| FPGA | E2E bitstream | GREEN | Yosys→nextpnr→prjxray→.bit (zero Vivado) | +| FPGA | Yosys synthesis | RED | `fpga-synthesis` CI job failing; last green 2026-04-14. Local `gen-verilog` smoke still passes 5/5 | +| FPGA | E2E bitstream | RED | Yosys→nextpnr→prjxray→.bit never validated in CI: `fpga-build.yml` is 36 success / 842 failure / 3 cancelled over 881 runs, and `fpga-bitstream` is skipped behind `needs: fpga-synthesis` | | FPGA | Board profiles | GREEN | QMTECH XC7A100T (minimal+full), Arty A7 | | FPGA | `--profile` flag | GREEN | `--profile minimal|full` in fpga-build | | Pins | Pins IR | GREEN | `specs/pins/ir.t27` — conflict detection invariants | @@ -67,7 +67,7 @@ Discoverability mirror of the numeric corpus. GitHub remains the primary source | CI | Seal coverage | GREEN | All specs sealed | | CI | Schema validation | GREEN | Conformance vectors validated | | CI | FPGA smoke | GREEN | Verilog gen in CI | -| CI | FPGA bitstream artifact | GREEN | .bit uploaded per PR (7-day retention) | +| CI | FPGA bitstream artifact | RED | No .bit uploaded since 2026-04-14 — job skipped behind failing `fpga-synthesis` | | TRI | PHI LOOP CLI | GREEN | `cli/tri/` standalone binary | | TRI | MCP server | GREEN | `cli/tri-mcp/` — 10 tools over JSON-RPC | | Spec | Phase 3 (shell/tools/file) | YELLOW | 6/8 parse; 2 file specs have parser issue (#388) | diff --git a/bootstrap/src/main.rs b/bootstrap/src/main.rs index ab73a8efd9..6e8ca5212e 100644 --- a/bootstrap/src/main.rs +++ b/bootstrap/src/main.rs @@ -4934,7 +4934,7 @@ endmodule fs::write( &synth_script, format!( - "read_verilog {files}\nhierarchy -check -top {top}\nproc; opt; fsm; opt; memory; opt\nsynth_xilinx -top {top}\nwrite_json {json}\nstat\n", + "read_verilog -sv -DSIMULATION {files}\nhierarchy -check -top {top}\nproc; opt; fsm; opt; memory; opt\nsynth_xilinx -top {top}\nwrite_json {json}\nstat\n", files = verilog_files, top = top, json = synth_json.display(), @@ -4959,7 +4959,7 @@ endmodule fs::write( &synth_script, format!( - "read_verilog {files}\nhierarchy -check -top {top}\nproc; opt; fsm; opt; memory; opt\nsynth_xilinx -top {top}\nwrite_json {json}\nstat\n", + "read_verilog -sv -DSIMULATION {files}\nhierarchy -check -top {top}\nproc; opt; fsm; opt; memory; opt\nsynth_xilinx -top {top}\nwrite_json {json}\nstat\n", files = verilog_files, top = top, json = synth_json.display(), diff --git a/docs/arxiv-submission/trinity-gf16.tex b/docs/arxiv-submission/trinity-gf16.tex index 18307a2fd2..027d577971 100644 --- a/docs/arxiv-submission/trinity-gf16.tex +++ b/docs/arxiv-submission/trinity-gf16.tex @@ -293,7 +293,7 @@ \subsubsection{4.1 Platform}\label{platform} \begin{itemize} \tightlist \item - \textbf{FPGA:} QMTECH XC7A100T-1FGG676C (Artix-7, 126,800 LUTs, 240 + \textbf{FPGA:} QMTECH XC7A100T-1FGG676C (Artix-7, 63,400 LUTs, 240 DSP48E1) \item \textbf{Toolchain:} openXC7 (Yosys 0.62 + nextpnr-xilinx) diff --git a/docs/arxiv-trinity-gf16-draft.md b/docs/arxiv-trinity-gf16-draft.md index 5bc9f49e00..0cec34faba 100644 --- a/docs/arxiv-trinity-gf16-draft.md +++ b/docs/arxiv-trinity-gf16-draft.md @@ -113,7 +113,7 @@ C[i][j] = dot4(A[i][0:3], B[0:3][j]) ### 4.1 Platform -- **FPGA:** QMTECH XC7A100T-1FGG676C (Artix-7, 126,800 LUTs, 240 DSP48E1) +- **FPGA:** QMTECH XC7A100T-1FGG676C (Artix-7, 63,400 LUTs, 240 DSP48E1) - **Toolchain:** openXC7 (Yosys 0.62 + nextpnr-xilinx) - **Clock:** 20-stage ring oscillator (onboard M21 crystal non-functional) - **Programming:** XVC via ESP32 (192.168.1.30:2542) diff --git a/specs/numeric/formats_catalog.t27 b/specs/numeric/formats_catalog.t27 index ef2a83e79f..3abb33f84a 100644 --- a/specs/numeric/formats_catalog.t27 +++ b/specs/numeric/formats_catalog.t27 @@ -225,7 +225,7 @@ module FormatsCatalog { // CATALOG: id=gf12 name="GF12" bits=12 s=1 e=4 m=7 bias=7 phi_distance=0.047 storage=u16 cluster=GoldenFloat status=Verified standard="this work; L0/F3" use_case="mid-range / audio" gf_relation=self source="BENCH-007 (specs/numeric/gf12.t27)" fn gf12() -> str { return "gf12"; } - // CATALOG: id=gf16 name="GF16" bits=16 s=1 e=6 m=9 bias=31 phi_distance=0.049 storage=u16 cluster=GoldenFloat status=Verified standard="this work; PHI_BIAS=60; FPGA 35/35 at 323 MHz Artix-7" use_case="training and inference (production)" gf_relation=self source="specs/numeric/gf16.t27; zenodo 10.5281/zenodo.19227877 (HW archive)" + // CATALOG: id=gf16 name="GF16" bits=16 s=1 e=6 m=9 bias=31 phi_distance=0.049 storage=u16 cluster=GoldenFloat status=Verified standard="this work; PHI_BIAS=60" use_case="training and inference (production)" gf_relation=self source="specs/numeric/gf16.t27" fn gf16() -> str { return "gf16"; } // CATALOG: id=gf20 name="GF20" bits=20 s=1 e=7 m=12 bias=63 phi_distance=0.035 storage=u32 cluster=GoldenFloat status=Experimental standard="this work; 17-squared empirical PHI_BIAS=289" use_case="high-precision edge" gf_relation=self source="specs/numeric/gf20.t27 (spec only)"