Found while landing #2208: its two remaining failures are pre-existing, not the PR's. fpga-build.yml on master shows six consecutive failures back to 2026-08-08 and zero successes in the last ten runs — ten days before any of the current change series existed. Same shape as emit-bitexact was in #2184: red, and nothing surfacing it, because the paths: filter rarely triggers the workflow on PRs.
Failure 1 — fpga-formal, infra:
ERROR: Could not find a version that satisfies the requirement sby (from versions: none)
pip install sby — SymbiYosys is not installable under that name from PyPI. Identical error in the 2026-08-09 master run.
Failure 2 — fpga-synthesis, codegen trait:
build/fpga/generated/mac.v:535: ERROR: Failed to evaluate system task $display' with non-constant argument
The generator emits bench blocks as initial begin ... $display("[BENCH] ... %%0d cycles", _bench_cycles); end under ifndef SIMULATION — so synthesis sees an initial $display with a non-constant argument, which Yosys evaluates at elaboration and rejects. (The doubled %% also means the format prints literally rather than formatting — a second, smaller oddity in the same line.) Reproduced locally from specs/fpga/mac.t27 at line 535 of fresh output.
Neither is touched by #2208's diff (tokens/lexer/parser/extra_op sites/cast diagnostic — no bench emission).
Also worth fixing while here: neither job carries timeout-minutes, and on 2026-08-18 the Install Icarus Verilog + Yosys apt step hung for 6h0m16s — the GitHub ceiling — reading as a red PR while the PR's own steps were all skipped. Every job in this workflow should have a timeout.
Refs #2210
Found while landing #2208: its two remaining failures are pre-existing, not the PR's.
fpga-build.ymlon master shows six consecutive failures back to 2026-08-08 and zero successes in the last ten runs — ten days before any of the current change series existed. Same shape asemit-bitexactwas in #2184: red, and nothing surfacing it, because thepaths:filter rarely triggers the workflow on PRs.Failure 1 —
fpga-formal, infra:pip install sby— SymbiYosys is not installable under that name from PyPI. Identical error in the 2026-08-09 master run.Failure 2 —
fpga-synthesis, codegen trait:The generator emits bench blocks as
initial begin ... $display("[BENCH] ... %%0d cycles", _bench_cycles); endunderifndef SIMULATION— so synthesis sees aninitial$displaywith a non-constant argument, which Yosys evaluates at elaboration and rejects. (The doubled%%also means the format prints literally rather than formatting — a second, smaller oddity in the same line.) Reproduced locally fromspecs/fpga/mac.t27at line 535 of fresh output.Neither is touched by #2208's diff (tokens/lexer/parser/extra_op sites/cast diagnostic — no bench emission).
Also worth fixing while here: neither job carries
timeout-minutes, and on 2026-08-18 theInstall Icarus Verilog + Yosysapt step hung for 6h0m16s — the GitHub ceiling — reading as a red PR while the PR's own steps were allskipped. Every job in this workflow should have a timeout.Refs #2210