Cross-target divergence in the C/Rust backends — red since 2026-08-14, seen 3 times in 10 days

[gHashTag]

tools/verify_igla_race.py reports IGLA RACE CROSS-TARGET MISMATCH and exits 1:

FAIL: C backend failed to build/run
FAIL: Rust backend failed to build/run
FAIL: systolic PE C failed to build/run
FAIL: systolic PE Rust failed to build/run

This is not new. The identical four lines appear in the 2026-08-14 run on w699-gate-topology (run 31843694525). The gate last passed 2026-08-08. Between those dates it ran zero times, and only three times in ten days — because its paths: filter did not include bootstrap/**, where all four backends live. The divergence has therefore been unproven, not absent, for at least four days.

The specific defects, from the script's own notes:

1. gen_rust emits a mixed-width add with no cast — i16 + i8. Rust rejects it; C silently promotes. That is a genuine semantic divergence between two targets the project claims are bit-exact, not a build-config problem.
2. systolic_ternary imports ternary_mul but the import is not emitted into its C/Rust output — a dangling call. The primitive currently has to be supplied from ternary_mac's core.
3. Emitter gaps on the full IGLA spec: slice .len(), duplicate test emission, serde deps, non-Copy struct.

Why it matters more than a red check. "One spec, four targets, bit-exact" is this repository's central claim. Item 1 is a case where two targets compute differently from the same spec — exactly what the gate exists to detect. It detected it four days ago and nobody saw, because almost nothing triggered the gate.

Exposed by #2183 / #2182, which makes the gate fire on compiler changes. That PR does not introduce this failure and does not fix it; it makes it visible. emit-bitexact is not in the required-checks table (docs/BRANCH-PROTECTION.md), so master going red here does not block other PRs.

Refs #2183

[gHashTag]

Corrected, and closing. There was no cross-target divergence.

The cause was one missing } in each of 27 spec files (#2185, merged as #2186). The spec did not parse, so no backend ever ran — and verify_igla_race.py reported that as FAIL: C backend failed to build/run, which is where this issue's framing came from.

With the braces closed, emit-bitexact passes in 7m05s:

OK ternary_mul/mac:      C == reference BIT-EXACT over 800 vectors
OK ternary_mul/mac:      Rust == reference BIT-EXACT over 800 vectors
OK systolic_ternary_pe:  C == reference BIT-EXACT over 800 vectors (i16 psum)
OK systolic_ternary_pe:  Rust == reference BIT-EXACT over 800 vectors (i16 psum)

What I got wrong here: I read FAIL: C backend failed to build/run plus the script's separate note about gen_rust emitting i16 + i8 without a cast, and concluded the two were the same fault — that a real semantic divergence was making the gate red. They are unrelated. The i16 + i8 gap is real, but the script works around it with a documented one-token replacement precisely so the arithmetic can still be cross-checked, and it was never what failed.

I should have read the compiler's own message before accepting the wrapper's summary. That message named the file, the function, the line and the token, and the wrapper discarded it (capture_output=True, returncode only).

Still open and worth tracking separately:

• the gen_rust mixed-width i16 + i8 emit gap (worked around, not fixed)
• systolic_ternary importing ternary_mul without the import being emitted — dangling call
• 15 of 27 igla specs still failing on unrelated parser features, overlapping parser: parameterised type application Name(T) in type position blocks 27 of 28 ADR-008 specs #2174