gen-verilog: u64 width truncation in lowered helper functions (surfaced by icarus assert lowering)

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With #1885's assert lowering in place, t27c icarus-simulate on tri-net's specs/tri_gft_arith.t27 compiles and runs -- and every GF-T32 u64-helper test block now FAILS in simulation while the same functions are correct in gen-rust and in the hand-written silicon KATs:

[TEST] gft32_multiply : FAILED
  assert failed: GF-T32 1.0*1.0 no carry
  assert failed: GF-T32 unity mantissa 0
  assert failed: GF-T32 unity*unity = offset 364, mant 0
  assert failed: GF-T32 1.5*1.5 -> mantissa 2^22
  assert failed: GF-T32 1.5*1.5 = offset 365, mant 2^22

Failing calls are the *_u64 helpers (e.g. gft_mul_mant_carry_u64(16777216, 16777216, 33554432), verify_gft_mul_full_u64(364, 16777216, 364, 16777216, 365, 4194304, 364, 728, 33554432)): mantissa products reach 2^48, so any 32-bit reg/wire lowering of a u64 local or parameter truncates them. Same defect family as ff0b8de "u64 comparison operands truncated to u32 in gen-rust", but in the Verilog backend. The smaller-width per-rung tests in the same spec PASS, which points at width assignment for u64 params/locals rather than the arithmetic itself.

Repro: build t27c >= #1885, then t27c icarus-simulate <tri-net>/specs/tri_gft_arith.t27.